公开(公告)号：US5406096A

公开(公告)日：1995-04-11

申请号：US194771

申请日：1994-02-09

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/12 ,  H03K17/10 ,  H03K17/687 ,  H03K17/08 ,  H01L27/02 ,  H03K17/689

CPC分类号： H03K17/102 ,  H01L27/0688 ,  H01L27/088

摘要： A high voltage device (10) having MOS input characteristics. A low voltage MOS transistor (12) is provided which has a source (18), a drain (22), and a gate (25). A high voltage transistor (14) is also provided which has a source (20), a drain (24), and gate (16). The source (18) of the low voltage MOS transistor (12) is connected to the gate (16) of the high voltage transistor (14). The drain (22) of the low voltage MOS transistor (12)is connected to the source (20)of the high voltage transistor The low voltage MOS transistor (12) may have a silicon substrate and the substrate of the high voltage transistor (14)may comprise silicon, silicon carbide, or gallium arsenide.

摘要翻译： 具有MOS输入特性的高电压装置（10）。 提供了具有源极（18），漏极（22）和栅极（25）的低电压MOS晶体管（12）。 还提供了具有源极（20），漏极（24）和栅极（16）的高压晶体管（14）。 低电压MOS晶体管（12）的源极（18）连接到高压晶体管（14）的栅极（16）。 低电压MOS晶体管（12）的漏极（22）与高电压晶体管的源极（20）连接。低压MOS晶体管（12）可以具有硅衬底和高压晶体管（14）的衬底 ）可以包括硅，碳化硅或砷化镓。

公开(公告)号：US5393999A

公开(公告)日：1995-02-28

申请号：US257500

申请日：1994-06-09

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/161 ,  H01L29/20

CPC分类号： H01L29/1608 ,  H01L29/4175 ,  H01L29/66068 ,  H01L29/1087

摘要： A MOSFET (100) device having a silicon carbide substrate (102) of a first conductivity type. A first epitaxial layer (104) of said first conductivity type and a second epitaxial layer (106) of a second conductivity type are located on a top side of the substrate (102). An insulator layer (108) separates gate electrode (112) from second epitaxial layer (106). A drift region (118) of the first conductivity type is located within the second epitaxial layer (106) on the first side of the gate electrode (112). The drift region has an extension which extends through the second epitaxial layer (106) to the first epitaxial layer (104). Source regions (116) and body contact regions (122) are located within the second epitaxial layer (106) on the second side of the gate electrode (112). Source regions (116,) and body contact regions (122) are of opposite conductivity type. Source electrode (126) electrically connects source regions (116) and body contact regions (122 ). A drain electrode (128) is located on a bottom side of the substrate.

摘要翻译： 一种具有第一导电类型的碳化硅衬底（102）的MOSFET（100）器件。 所述第一导电类型的第一外延层（104）和第二导电类型的第二外延层（106）位于所述基板（102）的顶侧。 绝缘体层（108）将栅电极（112）与第二外延层（106）分离。 第一导电类型的漂移区域（118）位于栅电极（112）的第一侧上的第二外延层（106）内。 漂移区具有延伸穿过第二外延层（106）到第一外延层（104）的延伸。 源极区（116）和体接触区（122）位于栅电极（112）的第二侧上的第二外延层（106）内。 源极区（116）和体接触区（122）具有相反的导电类型。 源极（126）电连接源区（116）和体接触区（122）。 漏电极（128）位于衬底的底侧。

公开(公告)号：US5382535A

公开(公告)日：1995-01-17

申请号：US213887

申请日：1994-03-16

申请人： Satwinder Malhi ,  Wai T. Ng

发明人： Satwinder Malhi ,  Wai T. Ng

IPC分类号： H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7835 ,  H01L29/7801

摘要： A transistor has a JFET gate region of a first conductivity type formed at the face of a semiconductor layer to laterally and downwardly surround a drift region of a second conductivity type. A thick insulator region is formed on a portion of the drift region at the face. A IGFET body of the first conductivity type is formed at the face to be adjacent the JFET gate region. This body spaces a source region of the second conductivity type from the drift region. A drain region is formed at the face to be of the second conductivity type and to adjoin the drift region, and to be spaced from the IGFET body. A conductive gate extends over the face between the source region and the thick insulator region, with a thin gate insulator spacing the gate from the IGFET body. The enhanced doping concentration of the JFET gate region with respect to the semiconductor layer allows the dopant concentration of the drift region to likewise be increased, thereby allowing RESURF conditions to be met at the rated voltage and with a lower r.sub.ds (on).

摘要翻译： 晶体管具有在半导体层的表面形成的第一导电类型的JFET栅极区域，以横向和向下包围第二导电类型的漂移区域。 在该表面的漂移区域的一部分上形成厚的绝缘体区域。 在与JFET栅极区域相邻的面处形成第一导电类型的IGFET主体。 本体从漂移区域排出第二导电类型的源极区域。 漏极区域形成在第二导电类型的表面并与漂移区相邻并且与IGFET本体间隔开。 导电栅极在源极区域和厚的绝缘体区域之间的表面上延伸，薄栅极绝缘体将栅极与IGFET主体间隔开。 JFET栅极区域相对于半导体层的增强的掺杂浓度允许漂移区域的掺杂剂浓度同样增加，从而允许在额定电压和较低rds（on）下满足RESURF条件。

公开(公告)号：US5187020A

公开(公告)日：1993-02-16

申请号：US745994

申请日：1991-11-05

申请人： Oh-Kyong Kwon ,  Satwinder Malhi ,  Masahi Hashimoto

发明人： Oh-Kyong Kwon ,  Satwinder Malhi ,  Masahi Hashimoto

IPC分类号： G01R1/073 ,  H01L21/60 ,  H01L21/68 ,  H01L23/498 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40

CPC分类号： H01R13/2414 ,  G01R1/0735 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/81 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/325 ,  H05K3/4007 ,  Y10S428/901 ,  Y10S439/908 ,  Y10S439/912 ,  Y10T428/12396 ,  Y10T428/12569

摘要： A contact pad including a compliant, electrically conductive polymer is provided in a substrate. The contact pad may include a metallic base, and a metallic upper surface wherein said polymer is intermediate said base and upper surfaces. The pad also may have a recessed upper surface, or have a metallic bump thereon depending upon the specific use intended. The contact pad may be incorporated into a substrate including a base substrate material having an upper surface, an interconnecting layer on the upper surface, a dielectric layer on the interconnecting layer, and at least one compliant, electrically conductive polymeric contact pad extending through the dielectric layer and in contact with the interconnecting layer. The substrate so formed may be a temporary substrate used, for example, in testing of integrated circuit chips. The contact pads are manufactured on a substrate by metallizing the surface of a substrate to form an interconnect layer, coating the interconnect layer with a dielectric layer, patterning the sites of the contact pads on the dielectric layer to selectively expose metallic pad portions of the interconnect layer, and coating the exposed portions of the interconnect layer with a compliant, electrically conductive polymer. Alternatively, the manufacturing may include the steps of metallizing the surface of a substrate to form an interconnect layer, coating a polymer layer on the interconnect layer, defining a metal diffusion mask to establish a pattern for the pad, diffusing conductive metal into the layer as defined by the diffusion mask to provide regions of the polymer layer having metal diffused therein, and stripping the diffusion mask. The polymer may be either conductive or non-conductive when the coating step occurs.

摘要翻译： 在衬底中提供包括柔性导电聚合物的接触焊盘。 接触垫可以包括金属基底和金属上表面，其中所述聚合物在所述基底和上表面之间。 该垫还可以具有凹陷的上表面，或者在其上具有金属凸块，这取决于具体的用途。 接触焊盘可以结合到包括具有上表面的基底材料，上表面上的互连层，互连层上的介电层以及延伸穿过电介质的至少一个顺从的导电聚合物接触焊盘的衬底中 并与互连层接触。 这样形成的基板可以是例如在集成电路芯片的测试中使用的临时衬底。 接触垫通过金属化衬底的表面以形成互连层而制成在衬底上，用互连层涂覆互连层，使电介质层上的接触焊盘的位置图案化，以选择性地暴露互连的金属焊盘部分 层，并用柔性导电聚合物涂覆互连层的暴露部分。 或者，制造可以包括以下步骤：金属化基板的表面以形成互连层，在互连层上涂覆聚合物层，限定金属扩散掩模以建立用于焊盘的图案，将导电金属扩散到该层中作为 由扩散掩模限定以提供具有在其中扩散的金属的聚合物层的区域，并剥离扩散掩模。 当涂覆步骤发生时，聚合物可以是导电的或非导电的。

公开(公告)号：US5090118A

公开(公告)日：1992-02-25

申请号：US560398

申请日：1990-07-31

申请人： On-Kyong Kwon ,  Masashi Hashimoto ,  Satwinder Malhi

发明人： On-Kyong Kwon ,  Masashi Hashimoto ,  Satwinder Malhi

IPC分类号： G01R1/073 ,  G01R31/28 ,  H01R12/04

CPC分类号： G01R31/2886 ,  G01R1/0735 ,  Y10T29/49149 ,  Y10T29/49155

摘要： A high performance test head (18) communicates test signals between integrated circuit test pads and integrated circuit tester. Test head (18) comprises metal bumps (22) that electrically couple with test pads to communicate test signals between test pads and test circuitry. Planar foundation plate (30) provides structural support. Compliant material layer (26) associates with metal bumps (22) and compresses to assure positive contact between metal bumps (22) and test pads. Compliant material layer (26) is positioned between foundation plate (30) and metal bumps (22). Interconnection line (20) adjoins test head (18) to connect metal bumps (22) between test circuitry and integrated circuits. The present invention includes a method for high performance communication of test signals between test pads and test circuitry. The present invention further includes the method of applying semiconductor device fabrication techniques to produce a high performance test head (18).

摘要翻译： 高性能测试头（18）在集成电路测试焊盘和集成电路测试仪之间通信测试信号。 测试头（18）包括与测试焊盘电耦合以在测试焊盘和测试电路之间传送测试信号的金属凸块（22）。 平面基础板（30）提供结构支撑。 合适的材料层（26）与金属凸块（22）相关并且压缩以确保金属凸块（22）和测试垫之间的正接触。 合适的材料层（26）位于基板（30）和金属凸块（22）之间。 互连线（20）邻接测试头（18）以在测试电路和集成电路之间连接金属凸块（22）。 本发明包括用于测试焊盘和测试电路之间的测试信号的高性能通信的方法。 本发明还包括施加半导体器件制造技术以产生高性能测试头（18）的方法。

公开(公告)号：US5073117A

公开(公告)日：1991-12-17

申请号：US620221

申请日：1990-12-27

申请人： Satwinder Malhi ,  Oh K. Kwon ,  Shivaling S. Mahant-Shetti

发明人： Satwinder Malhi ,  Oh K. Kwon ,  Shivaling S. Mahant-Shetti

IPC分类号： G01R1/04 ,  H05K7/10

CPC分类号： H05K7/1061 ,  G01R1/0483 ,  G01R1/06727 ,  Y10S439/912 ,  Y10T29/49004 ,  Y10T29/4913

摘要： A test set socket adaptor (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adaptor (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate for variations in solder bumps (26) on the bare chip (22). The deflection of the cantilever beams (32) allows a positive contact between the solder bumps (26) and the cantilever beams for an AC and a burn-in test.

摘要翻译： 测试套筒适配器（20）包括基板（28），多个悬臂梁（32）和封装件（30）。 可以将裸芯片（22）插入并由测试插座适配器（20）保持，以插入到标准测试插座中。 悬臂（32）被设计成偏转和补偿裸芯片（22）上的焊料凸块（26）的变化。 悬臂梁（32）的偏转允许焊料凸块（26）和悬臂梁之间的正接触用于交流和老化测试。

公开(公告)号：US5006792A

公开(公告)日：1991-04-09

申请号：US330839

申请日：1989-03-30

申请人： Satwinder Malhi ,  Oh K. Kwon ,  Shivaling S. Mahant-Shetti

发明人： Satwinder Malhi ,  Oh K. Kwon ,  Shivaling S. Mahant-Shetti

IPC分类号： G01R31/26 ,  G01R1/04 ,  H01L21/66 ,  H05K7/10

CPC分类号： H05K7/1061 ,  G01R1/0483 ,  G01R1/06727

摘要： A test set socket adapter (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adapter (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate for variations in solder bumps (26) on the bare chip (22). The deflection of the cantilever beams (32) allows a positive contact between the solder bumps (26) and the cantilever beams for an AC and a burn-in test.

摘要翻译： 测试套筒适配器（20）包括基板（28），多个悬臂梁（32）和封装件（30）。 可以将裸芯片（22）插入并由测试插座适配器（20）保持，以插入到标准测试插座中。 悬臂（32）被设计成偏转和补偿裸芯片（22）上的焊料凸块（26）的变化。 悬臂梁（32）的偏转允许焊料凸块（26）和悬臂梁之间的正接触用于交流和老化测试。

公开(公告)号：US4502202A

公开(公告)日：1985-03-05

申请号：US505155

申请日：1983-06-17

申请人： Satwinder Malhi

发明人： Satwinder Malhi

IPC分类号： H01L27/00 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/00

CPC分类号： H01L21/8221

摘要： In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.

摘要翻译： 在堆叠CMOS中，使用第一级多晶硅中的单个栅极来寻址衬底中的n沟道器件和覆盖的p沟道器件。 p沟道多晶硅器件通过在栅极的侧壁处使用掺杂硼的氧化物将其沟道自对准到栅极。 该硼掺杂氧化物提供掺杂源，其掺杂第二多晶硅层以提供重掺杂的源极/漏极延伸区域，其在第一聚合物中与栅极自对准。 仍然需要掩模级别对源极和漏极进行图案化，但是自对准源极/漏极扩展区域意味着源极/漏极掩模级别可以具有合理的对准公差。