公开(公告)号：US20110089430A1

公开(公告)日：2011-04-21

申请号：US12926990

申请日：2010-12-22

Applicant: Toshihide Kikkawa

Inventor： Toshihide Kikkawa

IPC: H01L29/772

CPC classification number: H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

公开(公告)号：US07859020B2

公开(公告)日：2010-12-28

申请号：US12173392

申请日：2008-07-15

Applicant: Toshihide Kikkawa ,  Kenji Imanishi

Inventor： Toshihide Kikkawa ,  Kenji Imanishi

IPC: H01L31/072

CPC classification number: H03F1/0288 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/7787 ,  H03F2200/15 ,  H03F2200/451 ,  H03F2200/543

Abstract: A nitride semiconductor device includes a substrate, a stacked semiconductor structure formed over the substrate and including a electron channel layer of an undoped nitride semiconductor and an electron supplying layer of an n-type nitride semiconductor formed epitaxially over the electron channel layer, the n-type nitride semiconductor having an electron affinity smaller than an electron affinity of said undoped nitride semiconductor and a two-dimensional electron gas being formed in the electron channel layer along an interface to the electron supply layer, a gate electrode formed over the stacked semiconductor structure in correspondence to a channel region, and source and drain electrodes formed over the stacked semiconductor structure in ohmic contact therewith respectively at a first side and a second side of the gate electrode, the stacked semiconductor structure including, between the substrate and the electron channel layer, an n-type conductive layer and a barrier layer containing Al formed consecutively and epitaxially.

Abstract translation: 氮化物半导体器件包括衬底，在衬底上形成的堆叠半导体结构，并且包括在电子沟道层外部形成的非掺杂氮化物半导体的电子沟道层和n型氮化物半导体的电子供给层， 具有小于所述未掺杂的氮化物半导体的电子亲和力的电子亲和力的二次电子气体和沿着与电子供应层的界面在电子通道层中形成的二维电子气的氮化物半导体，形成在堆叠半导体结构上的栅电极 对应于沟道区，以及源极和漏极，其形成在层叠的半导体结构上，分别与栅电极的第一侧和第二侧欧姆接触，该层叠半导体结构包括在衬底和电子通道层之间， n型导电层和阻挡层 aining铝连续形成和外延形成。

公开(公告)号：US20100311233A1

公开(公告)日：2010-12-09

申请号：US12805506

申请日：2010-08-03

Applicant: Masahito Kanamura ,  Toshihide Kikkawa

Inventor： Masahito Kanamura ,  Toshihide Kikkawa

IPC: H01L21/28

CPC classification number: H01L29/41 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787

Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

Abstract translation: 在MIS型GaN-FET中，作为氮化物半导体层，在作为氮化物半导体层的表面层上设置由不含氧的导电性氮化物构成的基底层Ta N，以覆盖栅极绝缘体的下表面的至少一部分 由Ta2O5制成的薄膜在栅电极下。

公开(公告)号：US07800133B2

公开(公告)日：2010-09-21

申请号：US12068796

申请日：2008-02-12

Applicant: Masahito Kanamura ,  Toshihide Kikkawa

Inventor： Masahito Kanamura ,  Toshihide Kikkawa

IPC: H01L29/20

CPC classification number: H01L29/41 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787

Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

Abstract translation: 在MIS型GaN-FET中，作为氮化物半导体层，在作为氮化物半导体层的表面层上设置由不含氧的导电性氮化物构成的基底层Ta N，以覆盖栅极绝缘体的下表面的至少一部分 由Ta2O5制成的薄膜在栅电极下。

公开(公告)号：US07777251B2

公开(公告)日：2010-08-17

申请号：US12591574

申请日：2009-11-24

Applicant: Toshihide Kikkawa ,  Kenji Imanishi

Inventor： Toshihide Kikkawa ,  Kenji Imanishi

IPC: H01L29/80

CPC classification number: H01L29/7785 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H03F1/0288

Abstract: A lower electron supply layer is disposed over a lower electron transport layer made of compound semiconductor. The lower electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the lower electron transport layer. An upper electron transport layer is disposed over the lower electron supply layer. The upper electron transport layer is made of compound semiconductor having a doping concentration lower than that of the lower electron supply layer or non-doped compound semiconductor. An upper electron supply layer is disposed over the upper electron transport layer. The upper electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the upper electron transport layer. A source and drain electrodes are disposed over the upper electron supply layer. A gate electrode is disposed over the upper electron supply layer between the source and drain electrodes.

Abstract translation: 较低的电子供应层设置在由化合物半导体制成的较低电子传输层上。 较低的电子供应层由电子亲和力小于低电子传输层的n型化合物半导体制成。 上电子传输层设置在下电子供应层上。 上部电子传输层由具有低于下部电子供给层或非掺杂化合物半导体的掺杂浓度的化合物半导体制成。 上电子供给层设置在上电子传输层上。 上电子供给层由电子亲和力小于上电子传输层的n型化合物半导体制成。 源电极和漏电极设置在上电子供应层上。 栅电极设置在源电极和漏电极之间的上电子供应层上。

公开(公告)号：US07638819B2

公开(公告)日：2009-12-29

申请号：US11181730

申请日：2005-07-15

Applicant: Toshihide Kikkawa ,  Kenji Imanishi

Inventor： Toshihide Kikkawa ,  Kenji Imanishi

IPC: H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003

Abstract: A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge.

Abstract translation: GaN层用作电子转移层，并且形成为至少在其一部分中通过光致发光测量获得的A / B比为0.2以下，其中“A”是500nm的发光强度， 600nm带，“B”是GaN带边缘处的发光强度。

公开(公告)号：US20090170249A1

公开(公告)日：2009-07-02

申请号：US12318577

申请日：2008-12-31

Applicant: Toshihide Kikkawa

Inventor： Toshihide Kikkawa

IPC: H01L21/335

CPC classification number: H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract translation: 化合物半导体器件包括形成在SiC衬底10上的i-GaN缓冲层12; 形成在i-GaN缓冲层12上的n-AlGaN电子供给层16; 形成在n-AlGaN电子供给层16上的n-GaN帽层18; 形成在n-GaN覆盖层18上的源电极20和漏电极22; 形成在源电极20和漏电极22之间的n-GaN覆盖层18上的栅电极26; 形成在源电极20和漏电极22之间的n-GaN覆盖层18上的第一保护层24; 以及第二保护层30，该第二保护层30形成在栅电极26和漏电极22之间的第一保护层24中的开口28中，直到n-GaN覆盖层18，并且由不同于第一保护层的绝缘膜形成。

公开(公告)号：US20080197359A1

公开(公告)日：2008-08-21

申请号：US12034273

申请日：2008-02-20

Applicant: Kenji IMANISHI ,  Toshihide KIKKAWA

Inventor： Kenji IMANISHI ,  Toshihide KIKKAWA

IPC: H01L29/267 ,  H01L21/338

CPC classification number: H01L29/66431 ,  H01L21/02378 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/107 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/2203 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/812

Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0

Abstract translation: 化合物半导体器件具有形成在导电性SiC衬底上的缓冲层，形成在缓冲层上的Al x Ga 1-x N层，其中添加用于降低来自无意掺杂的施主杂质的载流子浓度的杂质，其中Al组分x为0

公开(公告)号：US5751028A

公开(公告)日：1998-05-12

申请号：US625704

申请日：1996-04-03

Applicant: Toshihide Kikkawa

Inventor： Toshihide Kikkawa

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/335 ,  H01L21/338 ,  H01L29/06 ,  H01L29/205 ,  H01L29/737 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328

CPC classification number: H01L29/66318 ,  H01L29/0657 ,  H01L29/66462 ,  H01L29/7783

Abstract: A compound semiconductor device includes a compound semiconductor layer having an upper major surface formed with a multi-step structure, wherein said multi-step structure includes a plurality of steps each having a step height of at least 5 atomic layers and a step width of 300 nm or more.

Abstract translation: 化合物半导体器件包括具有形成有多级结构的上主表面的化合物半导体层，其中所述多步结构包括多个步骤，每个步骤的步长为至少5个原子层，步长为300 nm以上。

公开(公告)号：US08912571B2

公开(公告)日：2014-12-16

申请号：US13294654

申请日：2011-11-11

Applicant: Masahito Kanamura ,  Toshihide Kikkawa ,  Kenji Imanishi

Inventor： Masahito Kanamura ,  Toshihide Kikkawa ,  Kenji Imanishi

IPC: H01L29/66 ,  H01L21/338 ,  H01L29/51 ,  H01L29/778 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/513 ,  H01L29/66462

Abstract: A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film.

Abstract translation: 化合物半导体器件包括：化合物半导体层; 形成在所述化合物半导体层上的第一膜，所述第一膜在与所述化合物半导体层的界面处于带负电状态或非带电状态; 形成在所述第一膜上的第二膜，所述第二膜在与所述第一膜的界面处于带电状态; 以及嵌入到形成在第二膜中的开口中的栅电极。