公开(公告)号：US20110309467A1

公开(公告)日：2011-12-22

申请号：US13141332

申请日：2009-11-25

申请人： Shin Matsumoto ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Kenshi Tada

发明人： Shin Matsumoto ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Kenshi Tada

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L27/1266

摘要： Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).

摘要翻译： 公开了一种包括用于接合的基板（10a）的半导体器件和接合到基板（10a）的半导体元件部分（25aa），并且其中形成有元件图案（T），其中在 在基板（10a）和半导体元件部（25aa）中的至少一个上形成有基板（10a）和半导体元件部（25a），凹部（23a）。

公开(公告)号：US20100295105A1

公开(公告)日：2010-11-25

申请号：US12746323

申请日：2008-09-25

申请人： Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Yutaka Takafuji ,  Kenshi Tada ,  Michiko Takei

发明人： Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Yutaka Takafuji ,  Kenshi Tada ,  Michiko Takei

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L29/73 ,  H01L29/861 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.

摘要翻译： 一种制造半导体器件的方法包括：元件部分形成步骤，在基底层上形成元件部分; 在所述基底层中形成剥离层的剥离层形成工序; 键合步骤，将具有元件部分的基底层粘合到基底上; 以及分离步骤，通过加热结合到基板的基底层，沿着剥离层在深度方向上分离和去除基底层的一部分。 该方法还包括在分离步骤之后的离子注入步骤，用于在基底层中离子注入p型杂质元素，以调整元件的p型区域的杂质浓度。

公开(公告)号：US20100270618A1

公开(公告)日：2010-10-28

申请号：US12741852

申请日：2008-10-14

申请人： Michiko Takei ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Steven Roy Droes

发明人： Michiko Takei ,  Yutaka Takafuji ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Steven Roy Droes

IPC分类号： H01L29/786 ,  H01L21/762 ,  H01L23/48

CPC分类号： H01L27/1266 ,  H01L21/31053 ,  H01L21/76819 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a production method of a semiconductor device, capable of improving surface flatness of a semiconductor chip formed on a semiconductor substrate and thereby suppressing a variation in electrical characteristics of the semiconductor chip transferred onto a substrate with an insulating surface, and further capable of improving production yield. The present invention provides a production method of a semiconductor device including a semiconductor chip on a substrate with an insulating surface, the semiconductor chip having a conductive pattern film, the production method including the following successive steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer. The present invention is also a semiconductor device produced by the production method.

摘要翻译： 本发明提供一种半导体器件的制造方法，其能够提高形成在半导体基板上的半导体芯片的表面平坦性，从而抑制转印到具有绝缘表面的基板上的半导体芯片的电特性的变化， 提高产量。 本发明提供一种半导体器件的制造方法，该半导体器件在具有绝缘表面的衬底上具有半导体芯片，该半导体芯片具有导电图案膜，该制造方法包括以下连续步骤：在半导体上形成第一绝缘膜 并且在形成在半导体衬底上的导电图案膜上，并且通过图案化在导电图案膜布置的区域中减小第一绝缘膜的厚度; 形成第二绝缘膜并抛光第二绝缘膜，从而形成平坦化膜; 通过平坦化的膜将用于裂解的物质注入到半导体衬底中，从而形成裂解层; 将半导体芯片转印到具有绝缘表面的基板上，使得与半导体基板相对的一侧的芯片表面附着在其上; 并将半导体衬底与解理层分离。 本发明也是通过该制造方法制造的半导体装置。

公开(公告)号：US20100252885A1

公开(公告)日：2010-10-07

申请号：US12742463

申请日：2008-09-19

申请人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kenshi Tada

发明人： Yasumori Fukushima ,  Yutaka Takafuji ,  Kenshi Tada

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L27/12 ,  H01L29/78603 ,  H01L29/78621

摘要： A semiconductor device (10) is formed by bonding a semiconductor substrate (1) including a CMOS transistor (3) to a glass substrate (2). The semiconductor substrate (1) is formed by partial separation at a separation layer. A P-type high concentration impurity region (39n) is formed in electric connection with a channel region (35n) of an NMOS transistor (3n) so that an electric potential of the channel region (35n) is fixed. The P-type high concentration impurity region (39n) has the same P conductive type as that of the channel region (35n) and also has a concentration higher than that of the channel region (35n). An N-type high concentration impurity region (39p) is formed in electric connection with a channel region (35p) of a PMOS transistor (3p) so that an electric potential of the channel region (35p) is fixed. The N-type high concentration impurity region (39p) has the same N conductive type as that of the channel region (35p) and also has a concentration higher than that of the channel region (35p). This makes it possible to provide a semiconductor device whose performance can be enhanced by restraint on variation in a characteristic of a thin film transistor and a display device including the semiconductor device.

摘要翻译： 半导体器件（10）通过将包括CMOS晶体管（3）的半导体衬底（1）结合到玻璃衬底（2）而形成。 半导体衬底（1）通过在分离层处的部分分离而形成。 形成与NMOS晶体管（3n）的沟道区（35n）电连接的P型高浓度杂质区（39n），使得沟道区（35n）的电位固定。 P型高浓度杂质区域（39n）具有与沟道区域（35n）相同的P导电型，并且其浓度高于沟道区域（35n）的浓度。 形成与PMOS晶体管（3p）的沟道区（35p）电连接的N型高浓度杂质区（39p），使得沟道区（35p）的电位固定。 N型高浓度杂质区（39p）具有与沟道区（35p）相同的N导电型，其浓度高于沟道区（35p）。 这使得可以提供一种通过限制薄膜晶体管的特性变化和包括半导体器件的显示装置来提高其性能的半导体器件。

公开(公告)号：US20100244136A1

公开(公告)日：2010-09-30

申请号：US12742660

申请日：2008-10-22

申请人： Yutaka Takafuji ,  Kazuo Nakagawa ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Michiko Takei

发明人： Yutaka Takafuji ,  Kazuo Nakagawa ,  Yasumori Fukushima ,  Kazuhide Tomiyasu ,  Michiko Takei

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/665 ,  H01L29/66772

摘要： The present invention provides a semiconductor device, a single-crystal semiconductor thin film-including substrate, and production methods thereof, each allowing single-crystal semiconductor thin film-including single-crystal semiconductor elements produced by being transferred onto a low heat resistant insulating substrate to have enhanced transistor characteristics and a reduced wiring resistance.The present invention is a production method of a semiconductor device including single-crystal semiconductor thin film-including single-crystal semiconductor elements on an insulating substrate,the production method including a heat treatment step of subjecting a single-crystal semiconductor thin film to a heat treatment at 650° C. or higher,the single-crystal semiconductor thin film including at least part of each one of single-crystal semiconductor elements and boded to an intermediate substrate with a heat-resistant temperature higher than that of the insulating substrate.

摘要翻译： 本发明提供一种半导体器件，含有单晶半导体薄膜的衬底及其制造方法，其中，通过转印到低耐热绝缘衬底上制造的包含单晶半导体薄膜的单晶半导体元件 具有增强的晶体管特性和降低的布线电阻。 本发明是一种在绝缘基板上包括单晶半导体薄膜的单晶半导体元件的半导体器件的制造方法，该制造方法包括对单晶半导体薄膜进行热处理的热处理工序 在650℃以上的处理，所述单晶半导体薄膜包含单晶半导体元件的至少一部分，并且与耐热温度高于绝缘基板的中间基板接合。

公开(公告)号：US07122830B2

公开(公告)日：2006-10-17

申请号：US10717562

申请日：2003-11-21

申请人： Akira Ishikawa ,  Yasumori Fukushima

发明人： Akira Ishikawa ,  Yasumori Fukushima

IPC分类号： H01L29/04 ,  H01L29/15

CPC分类号： G02F1/13454 ,  H01L27/124

摘要： The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.

摘要翻译： 本发明提供了一种半导体器件，其中相对于像素区域的外围电路区域的面积减小，并且提供了半导体器件的制造方法。 根据本发明的半导体器件的特征在于具有像素区域1，布置在像素区域的至少一部分周边的外围电路区域2 a至2 c以及形成在外围电路区域中的布线，以及 通过具有多层具有两层或更多层的布线。 多层布线的至少一层由低电阻材料形成。 晶体管形成在外围电路区域中，并且在晶体管的上侧形成具有两层或多层的多层布线。

公开(公告)号：US06888182B2

公开(公告)日：2005-05-03

申请号：US10389802

申请日：2003-03-18

申请人： Masahiro Mitani ,  Yasumori Fukushima

发明人： Masahiro Mitani ,  Yasumori Fukushima

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/148

CPC分类号： H01L29/78696 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

摘要： A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 μm, and the spacing is not less than 3 μm. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

摘要翻译： 本发明的薄膜晶体管具备：（i）形成在栅电极下方的多个分割沟道区，（ii）被分割的源极区域和分割的漏极区域，各分割沟道区域夹在其间， 源极区域彼此连接，并且分割的漏极区域彼此连接。 这里，分割的沟道区域被布置成使得分隔沟道区域之间的间隔小于作为一个分割沟道区域的宽度的沟道分割宽度，沟道分割宽度不大于50μm，并且间隔不是 少于3个妈妈。 利用这种布置，可以提供一种薄膜晶体管，其能够通过减小沟道区域的自发热以及能够减小布局面积的增加而降低阈值电压的变化而获得可靠性。

公开(公告)号：US06555448B2

公开(公告)日：2003-04-29

申请号：US09847313

申请日：2001-05-03

申请人： Yasumori Fukushima

发明人： Yasumori Fukushima

IPC分类号： H01L21322

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L21/3226 ,  H01L29/66757 ,  H01L29/78675

摘要： There is provided a semiconductor manufacturing method capable of sufficiently reducing catalytic element in a crystalline silicon film and also increasing the area of the crystalline silicon film to be left on the substrate. A catalytic element for accelerating the crystallization is introduced into an amorphous silicon film on a substrate, and a first heat treatment is performed to crystallize the amorphous silicon film into a crystalline silicon film. A mask layer is provided on the surface of the crystalline silicon film, the mask layer having an opening passing thicknesswise through the mask layer. Further thereon, a sacrifice film is formed so as to continuously cover the surface of the mask layer and an opening-correspondent portion of the crystalline silicon film. A getter element for gettering the catalytic element is introduced into the sacrifice film and the opening-correspondent portion of the crystalline silicon film. A second heat treatment is performed, by which the catalytic element is gettered from the crystalline silicon film to the sacrifice film through the opening.

摘要翻译： 提供了能够充分降低结晶硅膜中的催化元素并且还增加留在基板上的结晶硅膜的面积的半导体制造方法。 将用于加速结晶的催化元素引入到基板上的非晶硅膜中，并且进行第一热处理以将非晶硅膜结晶成晶体硅膜。 掩模层设置在结晶硅膜的表面上，掩模层具有穿过掩模层的厚度的开口。 此外，形成牺牲膜，以连续地覆盖掩模层的表面和结晶硅膜的开口部分。 将用于吸除催化元素的吸气元件引入牺牲膜和结晶硅膜的开口部分。 进行第二热处理，通过该第二热处理，催化元素通过开口从结晶硅膜吸收到牺牲膜。