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347 条记录 (耗时 0.023 秒)

    Makeup brush
    61.
    发明授权
    Makeup brush 失效
    化妆刷

    公开(公告)号：US5450865A

    公开(公告)日：1995-09-19

    申请号：US243086

    申请日：1994-05-16

    申请人： Young-Soo Park

    发明人： Young-Soo Park

    IPC分类号： A45D40/26 ,  A46B9/02

    CPC分类号： A45D40/265 ,  A46B9/02

    摘要： The present invention relates to a makeup brush such as an eyebrow brush, an eyeshadow brush or the like that is capable of providing sharp lines and/or gradation of makeup when applied. The makeup brush as embodied in the present invention generally includes a shank and a brush tuft mounted on an end of the shank. The width of the brush tuft along its top surface as viewed from a plan view of the top surface tapers such that the width of one end of the brush tuft is greater than the width of the second end. In one embodiment of the present invention, the top surface of the brush tuft is defined along a first plane that forms an acute angle with a second plane in which a base portion of the brush tuft. The apex of the acute angle is substantially located near the second end of the brush tuft.

    摘要翻译： 本发明涉及一种能够在使用时提供清晰线条和/或化妆等级的诸如眉刷，眼影刷等的化妆刷。 本发明中的化妆刷通常包括安装在柄端部上的柄和刷毛簇。 从顶表面的平面图看，刷毛束沿其顶表面的宽度逐渐变细，使得刷毛簇的一端的宽度大于第二端的宽度。 在本发明的一个实施例中，刷毛簇的顶表面沿着第一平面限定，第一平面与第二平面形成锐角，第二平面是刷毛束的基部。 锐角的顶点基本上位于刷毛簇的第二端附近。

    Microprocessor chip, data center, and computing system
    62.
    发明授权
    Microprocessor chip, data center, and computing system 有权
    微处理器芯片，数据中心和计算系统

    公开(公告)号：US09059808B2

    公开(公告)日：2015-06-16

    申请号：US13611839

    申请日：2012-09-12

    申请人： Ho-jung Kim ,  Young-soo Park

    发明人： Ho-jung Kim ,  Young-soo Park

    IPC分类号： H04B10/00 ,  H04B10/80

    CPC分类号： H04B10/801

    摘要： A microprocessor chip includes a plurality of processors; at least one first optical input/output unit configured to receive optical signals from an external device and transmit optical signals to the external device; and an optical system bus that is connected between the plurality of processors and the at least one first optical input/output unit.

    摘要翻译： 微处理器芯片包括多个处理器; 至少一个第一光输入/输出单元，被配置为从外部设备接收光信号并将光信号传输到所述外部设备; 以及连接在所述多个处理器与所述至少一个第一光学输入/输出单元之间的光学系统总线。

    Hybrid laser light sources for photonic integrated circuits
    63.
    发明授权
    Hybrid laser light sources for photonic integrated circuits 有权
    用于光子集成电路的混合激光光源

    公开(公告)号：US09042690B2

    公开(公告)日：2015-05-26

    申请号：US13614432

    申请日：2012-09-13

    申请人： Bok-ki Min ,  Taek Kim ,  Young-soo Park

    发明人： Bok-ki Min ,  Taek Kim ,  Young-soo Park

    IPC分类号： G02B6/34 ,  H01S3/08 ,  H01S5/183 ,  H01S3/00 ,  H01S5/20

    CPC分类号： H01S5/18358 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/1032 ,  H01S5/105 ,  H01S5/18325 ,  H01S5/18341 ,  H01S5/18361 ,  H01S5/1838 ,  H01S5/2018 ,  H01S5/2031

    摘要： A light source for a photonic integrated circuit may comprise a reflection coupling layer formed on a substrate in which an optical waveguide is provided, at least one side of the reflection coupling layer being optically connected to the optical waveguide; an optical mode alignment layer provided on the reflection coupling layer; and/or an upper structure provided on the optical mode alignment layer and including an active layer for generating light and a reflection layer provided on the active layer. A light source for a photonic integrated circuit may comprise a lower reflection layer; an optical waveguide optically connected to the lower reflection layer; an optical mode alignment layer on the lower reflection layer; an active layer on the optical mode alignment layer; and/or an upper reflection layer on the active layer.

    摘要翻译： 用于光子集成电路的光源可以包括形成在其中设置有光波导的基板上的反射耦合层，反射耦合层的至少一侧光学连接到光波导; 设置在反射耦合层上的光学模式取向层; 和/或设置在光学模式对准层上的上部结构，并且包括用于产生光的有源层和设置在有源层上的反射层。 光子集成电路的光源可以包括下反射层; 与下反射层光学连接的光波导; 在下反射层上的光学取向层; 光学对准层上的有源层; 和/或有源层上的上反射层。

    3D CMOS image sensors, sensor systems including the same
    64.
    发明授权
    3D CMOS image sensors, sensor systems including the same 有权
    3D CMOS图像传感器，传感器系统包括相同

    公开(公告)号：US09035309B2

    公开(公告)日：2015-05-19

    申请号：US12984972

    申请日：2011-01-05

    申请人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

    发明人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14629 ,  H01L27/14687

    摘要： A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

    摘要翻译： 一种三维（3D）CMOS图像传感器（CIS），其足以吸收入射的红外线（IR）并且包括形成在薄的外延膜中的红外线（IR）接收单元，由此容易地使用传统的CIS工艺 包括3D CIS的传感器系统和制造3D CIS的方法，3D CIS包括通过重复反射吸收入射到其中的IR的IR接收部分以产生电子 - 空穴对（EHP）; 以及形成在IR接收部上并且收集通过施加预定电压而产生的电子的电极部分。

    Semiconductor memory device and method of operating the same
    68.
    发明授权
    Semiconductor memory device and method of operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号：US08934303B2

    公开(公告)日：2015-01-13

    申请号：US13534540

    申请日：2012-06-27

    申请人： Young Soo Park

    发明人： Young Soo Park

    IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/24

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/24

    摘要： A semiconductor memory device is operated by, inter alia: precharging a bit line, providing a first voltage to a coupling circuit for coupling the bit lines and cell strings of a plurality of memory cells, providing a program voltage to a selected word line coupled to a memory cell on which a program operation will be performed among the plurality of memory cells, providing a pass voltage to unselected word lines, providing a second voltage lower than the first voltage to the coupling circuit, discharging the bit line by loading program data, and providing a third voltage lower than the second voltage to the coupling circuit.

    摘要翻译： 半导体存储器件尤其通过对位线进行预充电，向耦合电路提供第一电压，以耦合多个存储器单元的位线和单元串，从而将编程电压提供给所选择的字线 在多个存储单元中进行编程操作的存储单元，向未选择的字线提供通过电压，向耦合电路提供低于第一电压的第二电压，通过加载程序数据对位线进行放电， 并向耦合电路提供低于第二电压的第三电压。

    Semiconductor memory device
    69.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08897068B2

    公开(公告)日：2014-11-25

    申请号：US13452236

    申请日：2012-04-20

    申请人： Beom Sik Kim ,  Young Soo Park

    发明人： Beom Sik Kim ,  Young Soo Park

    IPC分类号： G11C16/04 ,  G11C16/34

    CPC分类号： G11C16/0483 ,  G11C16/3418

    摘要： A semiconductor memory device includes a memory cell array configured to include a plurality of memory blocks, a voltage generator configured to output operating voltages for data input and output to global lines, and a row decoder configured to transfer the operating voltages to local lines of a memory block, selected from among the plurality of memory blocks, and supply a ground voltage to local lines of unselected memory blocks in response to address signals.

    摘要翻译： 半导体存储器件包括被配置为包括多个存储器块的存储单元阵列，被配置为输出用于数据输入和输出到全局线的工作电压的电压发生器，以及配置成将工作电压传送到本地线的本地线的行解码器 存储器块，从多个存储器块中选择，并且响应于地址信号将接地电压提供给未选择的存储器块的本地线。

    Semiconductor memory device and method of erasing the same
    70.
    发明授权
    Semiconductor memory device and method of erasing the same 失效
    半导体存储器件及其擦除方法

    公开(公告)号：US08593882B2

    公开(公告)日：2013-11-26

    申请号：US13178786

    申请日：2011-07-08

    申请人： Young Soo Park

    发明人： Young Soo Park

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/14

    摘要： A semiconductor memory device includes memory cell blocks having physical pages coupled to memory cells, peripheral circuits configured to program the memory cells or read data stored in the memory cells, and a controller configured to control the peripheral circuits so that a pre-program is performed to make memory cells in the memory cell blocks have threshold voltages higher than a set voltage by programming memory cells of the selected memory cell block, having threshold voltages lower than the set voltage, in response to an erase command. The set voltage is an intermediate threshold voltage obtained from the threshold voltages of the memory cells of the selected memory cell block.

    摘要翻译： 半导体存储器件包括具有耦合到存储器单元的物理页面的存储单元块，被配置为对存储器单元进行编程或读取存储在存储单元中的数据的外围电路，以及控制器，被配置为控制外围电路，使得执行预编程 通过响应于擦除命令，通过编程具有低于设定电压的阈值电压的所选择的存储器单元块的存储单元来使存储单元块中的存储器单元具有高于设定电压的阈值电压。 设定电压是从所选存储单元块的存储单元的阈值电压获得的中间阈值电压。