公开(公告)号：US08063602B2

公开(公告)日：2011-11-22

申请号：US12202574

申请日：2008-09-02

申请人： Da Zhang ,  Hui Li ,  Emmanuel G. Collins

发明人： Da Zhang ,  Hui Li ,  Emmanuel G. Collins

IPC分类号： G05B11/42

CPC分类号： H02P21/0003

摘要： Different circuit-based implementations of stochastic anti-windup PI controllers are provided for a motor drive controller system. The designs can be implemented in a Field Programmable Gate Arrays (FPGA) device. The anti-windup PI controllers are implemented stochastically so as to enhance the computational capability of FPGA.

摘要翻译： 为电机驱动控制器系统提供了不同的基于电路的随机反卷积PI控制器的实现。 这些设计可以在现场可编程门阵列（FPGA）器件中实现。 防结块PI控制器随机实现，以提高FPGA的计算能力。

公开(公告)号：US20110187199A1

公开(公告)日：2011-08-04

申请号：US12674936

申请日：2007-12-26

申请人： Thomas Gietzold ,  Jeffrey J. Burchill ,  Da Zhang ,  Welqlan Hu

发明人： Thomas Gietzold ,  Jeffrey J. Burchill ,  Da Zhang ,  Welqlan Hu

IPC分类号： H02J4/00 ,  H02J7/00

CPC分类号： H02P9/02 ,  Y10T307/675

摘要： An apparatus and method for boosting output of a generator set are provided. The output of the generator set is connected to an electrical load. The apparatus includes an energy storage unit, and a power-electronic unit. The energy storage unit uses batteries and capacitors to store electric energy. The power-electronic unit measures an electrical parameter of the output of the generator set. Based on the measured electrical parameter and a predefined criterion, the power-electronic unit determines additional energy required by the electrical load. Thereafter, the power-electronic unit supplies the additional energy to the electrical load. The additional energy is drawn from the energy storage unit.

摘要翻译： 提供了一种用于提升发电机组的输出的装置和方法。 发电机组的输出连接到电气负载。 该装置包括能量存储单元和电力电子单元。 储能单元使用电池和电容器来储存电能。 电力电子单元测量发电机组输出的电气参数。 基于测量的电参数和预定标准，功率电子单元确定电负载所需的附加能量。 此后，电力电子单元向电负载提供额外的能量。 额外的能量从能量存储单元中抽出。

公开(公告)号：US20110180883A1

公开(公告)日：2011-07-28

申请号：US12695565

申请日：2010-01-28

申请人： Xiangdong Chen ,  Geng Wang ,  Da Zhang

发明人： Xiangdong Chen ,  Geng Wang ,  Da Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78

摘要： A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

摘要翻译： 一种方法和结构在衬底内注入第一种杂质以在衬底内邻近衬底的顶表面形成沟道区; 在通道区域上方的衬底的顶表面上形成栅极堆叠; 并且在所述衬底内注入第二类型杂质以在所述衬底内邻近所述顶表面形成源区和漏区。 沟道区域位于源区和漏区之间。 第二种杂质相对于第一种杂质具有相反的极性。 所述方法和结构相对于沟道区域内的第一类型杂质的浓度注入更大浓度的第一类型杂质，以在衬底下方（相对于顶表面）在通道内形成主体掺杂区域 地区; 并且在源极和漏极区域之下（相对于顶表面）下方的衬底内形成辅助体掺杂区域。

公开(公告)号：US07879666B2

公开(公告)日：2011-02-01

申请号：US12177986

申请日：2008-07-23

申请人： Da Zhang ,  Chendong Zhu ,  Xiangdong Chen ,  Melanie Sherony

发明人： Da Zhang ,  Chendong Zhu ,  Xiangdong Chen ,  Melanie Sherony

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L28/20

摘要： A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.

摘要翻译： 一种半导体工艺和装置，通过在栅极介电层（24）上形成金属基层（26）和半导体层（28），然后选择性地植入金属栅电极（30）和集成半导体电阻器（32） 电阻器区域（97）中的电阻器半导体层（28），以产生导电上部区域（46）和导电屏障（47），从而将电流流入电阻器半导体层（36）中仅限于顶部区域（46） 在最终形成的装置。

公开(公告)号：US07514313B2

公开(公告)日：2009-04-07

申请号：US11400945

申请日：2006-04-10

申请人： Omar Zia ,  Da Zhang ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Bich-Yen Nguyen

发明人： Omar Zia ,  Da Zhang ,  Venkat R. Kolagunta ,  Narayanan C. Ramani ,  Bich-Yen Nguyen

IPC分类号： H01L21/98 ,  H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

摘要翻译： 形成电子器件的工艺可以包括在第一和第二有源区上形成绝缘层和场隔离区。 该方法还可以包括形成种子层并暴露第一有源区。 该方法还可以包括分别在第一有源区和种子层上选择性地形成第一和第二半导体层。 第一和第二半导体层可以彼此间隔开。 在一个方面，该方法可以包括在基本相同的时间点同时选择性地形成第一和第二半导体层。 在另一方面，电子设备可以包括由场隔离区分隔开并由导电构件电连接的第一和第二晶体管结构。 设计为电浮置的半导体岛可以位于导电构件和基底层之间。

公开(公告)号：US20080206940A1

公开(公告)日：2008-08-28

申请号：US11680219

申请日：2007-02-28

申请人： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

发明人： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772

摘要： A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

摘要翻译： 在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。 第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。 在第一和第二区域上形成第一绝缘层。 第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。 从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。 半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。 在凹部中外延生长半导体材料。 去除第一绝缘层的剩余部分。

公开(公告)号：US20070235813A1

公开(公告)日：2007-10-11

申请号：US11400945

申请日：2006-04-10

申请人： Omar Zia ,  Da Zhang ,  Venkat Kolagunta ,  Narayanan Ramani ,  Bich-Yen Nguyen

发明人： Omar Zia ,  Da Zhang ,  Venkat Kolagunta ,  Narayanan Ramani ,  Bich-Yen Nguyen

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

摘要翻译： 形成电子器件的工艺可以包括在第一和第二有源区上形成绝缘层和场隔离区。 该方法还可以包括形成种子层并暴露第一有源区。 该方法还可以包括分别在第一有源区和种子层上选择性地形成第一和第二半导体层。 第一和第二半导体层可以彼此间隔开。 在一个方面，该方法可以包括在基本相同的时间点同时选择性地形成第一和第二半导体层。 在另一方面，电子设备可以包括由场隔离区分隔开并由导电构件电连接的第一和第二晶体管结构。 设计为电浮置的半导体岛可以位于导电构件和基底层之间。

公开(公告)号：US20070210314A1

公开(公告)日：2007-09-13

申请号：US11373536

申请日：2006-03-10

申请人： Brian Winstead ,  Ted White ,  Da Zhang

发明人： Brian Winstead ,  Ted White ,  Da Zhang

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

摘要翻译： 一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。 该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。 该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。 该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是 使用第二种材料创建。

公开(公告)号：US20070202651A1

公开(公告)日：2007-08-30

申请号：US11361171

申请日：2006-02-24

申请人： Da Zhang ,  Vance Adams ,  Bich-Yen Nguyen ,  Paul Grudowski

发明人： Da Zhang ,  Vance Adams ,  Bich-Yen Nguyen ,  Paul Grudowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

公开(公告)号：US20070184600A1

公开(公告)日：2007-08-09

申请号：US11348034

申请日：2006-02-06

申请人： Da Zhang ,  Michael Mendicino ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Michael Mendicino ,  Bich-Yen Nguyen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： Methods for forming portions of source and drain (S/D) regions of a first ensuing transistor (40) to include a semiconductor material (47) having a different composition of non-dopant elements than portions of S/D regions (35) of a second ensuing transistor (30) of opposite conductivity type are provided. The methods additionally include forming another semiconductor material (48) upon at least one set of the S/D regions of the ensuing transistors such that S/D surface layers of the ensuing transistors include substantially the same composition of non-dopant elements. A resulting semiconductor topography includes a pair of CMOS transistors (30, 40) collectively having S/D region surfaces with substantially the same composition of non-dopant elements. The S/D regions of one transistor (40) of the pair of CMOS transistors includes an underlying layer (47) having a different composition of non-dopant elements than underlying layers of the S/D regions (35) of the other transistor (30).

摘要翻译： 用于形成第一随后晶体管（40）的源极和漏极（S / D）区域的部分的方法，以包括具有与S / D区域（35）的部分不同的非掺杂元素的不同组成的半导体材料（47） 提供了具有相反导电类型的第二随后的晶体管（30）。 所述方法还包括在随后的晶体管的至少一组S / D区上形成另一半导体材料（48），使得随后的晶体管的S / D表面层包括基本上相同的非掺杂元素组成。 所得到的半导体形貌包括一对共同具有基本上相同组成的非掺杂元素的S / D区域表面的CMOS晶体管（30,40）。 该对CMOS晶体管的一个晶体管（40）的S / D区域包括与另一个晶体管的S / D区域（35）的下层不同的非掺杂元素组成的下层（47） 30）。