METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES
    61.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES 有权
    用自对准接触形成半导体器件的方法和结果器件

    公开(公告)号:US20140070285A1

    公开(公告)日:2014-03-13

    申请号:US13611652

    申请日:2012-09-12

    IPC分类号: H01L21/28 H01L29/78

    摘要: One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

    摘要翻译: 一种方法包括在衬底上形成牺牲栅极结构,形成邻近牺牲栅电极的第一侧壁间隔物,去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分,以及在衬底上形成衬层 牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。 该方法还包括在衬垫层之上形成绝缘材料的第一层,在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻,执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层, 暴露牺牲栅电极的上表面,去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔,以及在空腔中形成替换栅极结构。

    System and method of increasing poker tournament pools and number of payout positions
    64.
    发明授权
    System and method of increasing poker tournament pools and number of payout positions 有权
    增加扑克锦标赛池和支付职位数量的制度和方法

    公开(公告)号:US08449365B2

    公开(公告)日:2013-05-28

    申请号:US13532428

    申请日:2012-06-25

    IPC分类号: A63F9/24

    摘要: A second optional poker tournament fee allows participating players a chance to receive a payout when finishing the poker tournament in one of one or more extra bubble spots. So, if the player finishes close to the conventional bubble position the player may receive a payout if he or she paid the second optional fee. The number of extra spots is based on the number of second optional fees paid. In one version, if no players finish in the extra bubble spots the house collects the second optional fees as profits. In another version, the second optional fees, or a portion thereof, are used to increase the payouts associated with the conventional payout scheme independent of the second optional fees.

    摘要翻译: 第二个可选的扑克锦标赛费用允许参赛球员有机会在一个或多个额外的气泡点之一完成扑克锦标赛时获得支付。 因此,如果玩家完成接近传统的泡泡位置,玩家可以在支付第二个可选费用的情况下收到付款。 额外点数是根据支付的第二个可选费用的数量。 在一个版本中,如果没有玩家在额外的泡沫点完成,房子收取第二个可选费用作为利润。 在另一版本中,第二可选费用或其一部分用于增加与常规支付方案相关联的支付,而不依赖于第二可选费用。

    Gas turbine engine
    67.
    发明申请
    Gas turbine engine 失效
    燃气轮机

    公开(公告)号:US20100150705A1

    公开(公告)日:2010-06-17

    申请号:US12591260

    申请日:2009-11-13

    IPC分类号: F01D1/02

    摘要: A gas turbine engine (10) having a pressure-rise combustor (30) and the pressure-rise combustor (30) is positioned upstream of a stage of turbine nozzle guide vanes (32). The vanes (33) of the stage of turbine nozzle guide vanes (32) forms an ejector and each of the vanes (33) has an upstream portion (34) and a downstream portion (36). The upstream portions (34) of the vanes (33) have leading edges (38) and the upstream portions (34) are arranged substantially straight and parallel to define constant area mixing passages (40) for a flow of gases there-through. The downstream portions (36) of the vanes (33) are arranged at an angle to the upstream portions (34) of the vanes (33) to turn the flow of gases there-through.

    摘要翻译: 具有升压燃烧器(30)和升压燃烧器(30)的燃气涡轮发动机(10)位于涡轮喷嘴导叶(32)的一级的上游。 涡轮喷嘴引导叶片(32)的台阶叶片(33)形成喷射器,并且每个叶片(33)具有上游部分(34)和下游部分(36)。 叶片(33)的上游部分(34)具有前缘(38),并且上游部分(34)基本上直线且平行地布置,以限定用于气体流过的恒定区域混合通道(40)。 叶片(33)的下游部分(36)与叶片(33)的上游部分(34)成一定角度设置,以使气流通过。

    Spa apparatus
    69.
    发明授权
    Spa apparatus 失效
    水疗仪器

    公开(公告)号:US07490374B2

    公开(公告)日:2009-02-17

    申请号:US11394642

    申请日:2006-03-31

    IPC分类号: A47K3/022

    CPC分类号: A61H35/006 A61H2203/0431

    摘要: A spa apparatus includes an internal support structure having a front end and a rear end; a basin removably coupled and supported by the internal support structure proximate the front end, with the basin including a fluid circulation device; a seat coupled to the internal support structure, intermediate the basin and the rear end of the internal support structure; and at least a first and second shroud panel removably coupled to the internal support structure and configured to enclose a portion of the internal support structure.

    摘要翻译: 温泉设备包括具有前端和后端的内部支撑结构; 靠近前端由内部支撑结构可拆卸地联接和支撑的盆,盆具有流体循环装置; 连接到内部支撑结构的座,在内部支撑结构的盆和后端之间; 以及至少第一和第二护罩板,其可移除地联接到所述内部支撑结构并且构造成包围所述内部支撑结构的一部分。

    SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES
    70.
    发明申请
    SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES 有权
    用于具有共同逻辑设备的后盖控制SRAM的基板解决方案

    公开(公告)号:US20080258221A1

    公开(公告)日:2008-10-23

    申请号:US12144272

    申请日:2008-06-23

    IPC分类号: H01L27/11

    CPC分类号: H01L27/1108

    摘要: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

    摘要翻译: 一种半导体结构,其包括至少一个逻辑器件区域和至少一个静态随机存取存储器(SRAM)器件区域,其中每个器件区域包括双门控场效应晶体管(FET),其中每个FET器件的背栅极掺杂 提供了特定的水平,以提高不同器件区域内的FET器件的性能。 特别地,SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应,逻辑器件区域内的FET器件包括掺杂沟道,而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。