-
61.发明申请STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES 失效减少半导体器件中的电化学破碎和挤出效应的结构和方法公开(公告)号：US20120264295A1
公开(公告)日：2012-10-18
申请号：US13530999
申请日：2012-06-22
IPC分类号： H01L21/44
CPC分类号： H01L23/528 , H01L21/7682 , H01L21/76831 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。
-
62.发明授权公开(公告)号：US06417572B1
公开(公告)日：2002-07-09
申请号：US09354592
申请日：1999-07-16
申请人： Dureseti Chidambarrao , Ronald G. Filippi , Robert Rosenberg , Thomas M. Shaw , Timothy D. Sullivan , Richard A. Wachnik
发明人： Dureseti Chidambarrao , Ronald G. Filippi , Robert Rosenberg , Thomas M. Shaw , Timothy D. Sullivan , Richard A. Wachnik
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.
摘要翻译： 一种制造具有绝缘钝化层的金属互连的多电平半导体器件的方法和由此产生的产品。 该产品和工艺通过防止绝缘钝化层开裂而改善金属化互连对挤出 - 短电迁移故障的阻力。 该产品和工艺也降低电阻饱和度或电迁移引起的最大电阻偏移。 通过用绝缘钝化层包围的宽线金属化互连导电线，其两个或更多个狭窄的平行导线，其纵横比小于或等于位于其间的钝化层的单位，钝化裂纹和挤出 - 短路故障的发生率是 减少 该方法特别适用于多层布线结构，其中布线层具有由冗余金属化层，层间连接或两者引起的布线水平之间的扩散障碍。
-
公开(公告)号：US09105637B2
公开(公告)日：2015-08-11
申请号：US13475542
申请日：2012-05-18
IPC分类号： H01L23/52 , H01L21/768 , H01L23/525 , H01L27/10
CPC分类号： H01L23/5252 , H01L21/76807 , H01L21/76816 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A method including a first interconnect level including a first electrode embedded in a first dielectric layer, a top surface of the first electrode is substantially flush with a top surface of the first dielectric layer, a second interconnect level including a via embedded in a second dielectric layer above the first dielectric layer, a third dielectric layer in direct contact with and separating the first dielectric layer and the second dielectric layer, an entire top surface of the first electrode is in direct physical contact with a bottom surface of the third dielectric layer, and an interface between the first dielectric layer and the third dielectric layer extending from the top surface of the first electrode to the via, the interface including a length less than a minimum width of the via, a bottom surface of the via is in direct physical contact with the first dielectric layer.
摘要翻译： 一种包括第一互连电平的方法，包括嵌入在第一电介质层中的第一电极，第一电极的顶表面基本上与第一电介质层的顶表面平齐，第二互连电平包括嵌入第二电介质中的通孔 在与第一介电层和第二介电层直接接触和分离的第三电介质层上，第一电极的整个顶表面与第三电介质层的底表面直接物理接触， 以及从第一电极的顶表面延伸到通孔的第一介电层和第三电介质层之间的界面，所述界面包括小于通孔的最小宽度的长度，通孔的底表面是直接物理的 与第一电介质层接触。
-
64.发明授权Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices 失效减少半导体器件中电迁移破裂和挤出效应的结构和方法公开(公告)号：US08716101B2
公开(公告)日：2014-05-06
申请号：US13530999
申请日：2012-06-22
IPC分类号： H01L21/76
CPC分类号： H01L23/528 , H01L21/7682 , H01L21/76831 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.
摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在所述第二介电层中的空隙，停止在所述盖层上，其中所述空隙以这样的方式定位，以便隔离由于所述第一金属线的电迁移效应引起的结构损坏，所述效果包括一种或多种金属挤压 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。
-
公开(公告)号：US08455351B2
公开(公告)日：2013-06-04
申请号：US13531015
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中并且在其相对端处耦合到第一通孔的缓冲金属段。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。
-
公开(公告)号：US20120292763A1
公开(公告)日：2012-11-22
申请号：US13565416
申请日：2012-08-02
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。
-
公开(公告)号：US20120264289A1
公开(公告)日：2012-10-18
申请号：US13531015
申请日：2012-06-22
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。
-
公开(公告)号：US08237286B2
公开(公告)日：2012-08-07
申请号：US12760594
申请日：2010-04-15
申请人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
发明人： Hanyi Ding , Ronald G. Filippi , Jong-Ru Guo , Ping-Chuan Wang
IPC分类号： H01L23/522
CPC分类号： H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.
摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。
-
69.发明授权公开(公告)号：US07361584B2
公开(公告)日：2008-04-22
申请号：US10904329
申请日：2004-11-04
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/7688 , H01L22/24 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。
-
公开(公告)号：US06202191B1
公开(公告)日：2001-03-13
申请号：US09333604
申请日：1999-06-15
IPC分类号： G06F1750
CPC分类号： H01L21/76858 , G06F17/5077 , H01L21/76841 , H01L21/7685 , H01L23/5286 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a novel power grid structure for integrated circuit semiconductor chip devices that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array of conducting line elements with “phase shift” between adjacent tracks of segmented power busses. The novel grid structure includes a first metal layer including a first set of conducting line segments that are substantially parallel to one another and run in a first direction; a layer of diffusion blocking dielectric insulation above the first layer; a second metal layer including a second set of conducting line segments substantially parallel to each other and running in a second direction orthogonal to the first direction; and, interlevel contact studs disposed substantially vertically through the diffusion blocking dielectric insulation layer for electrically connecting aligned line segments of the first and second sets, wherein each segment of the first and second sets of line segments is limited to a predetermined length by a diffusion blocking boundary.
摘要翻译： 用于形成用于集成电路半导体芯片器件的新型电网结构的方法，其通过包括扩散阻挡层间接触并采用在分段功率总线的相邻轨道之间具有“相移”的导线组件的规则阵列来表现出增加的电迁移阻力。 新颖的栅格结构包括第一金属层，其包括基本上彼此平行并沿第一方向延伸的第一组导线段; 在第一层之上的一层扩散阻挡介电绝缘层; 第二金属层，包括基本上彼此平行并沿与第一方向正交的第二方向延伸的第二组导线段; 以及穿过所述扩散阻挡介电绝缘层基本垂直设置的层间接触柱，用于电连接所述第一和第二组的对准的线段，其中所述第一和第二组线段的每个段通过扩散阻挡被限制到预定长度 边界。
-
-
-
-
-
-
-
-
-
搜索结果
72 条记录 (耗时 0.037 秒)