公开(公告)号：US08772868B2

公开(公告)日：2014-07-08

申请号：US13095670

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley, Sr.

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley, Sr.

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/0243 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

摘要翻译： 功率器件包括具有多个交替布置的第一和第二导电类型的柱的半导体衬底。 第二导电类型的多个支柱中的至少一个包括设置在第二沟槽的沟槽侧壁上的第二导电类型的第一沟槽外延层和第二沟槽的沟槽底表面，第二沟槽外延层的第二沟槽外延层 设置在第二导电类型的第一沟槽外延层上的导电类型，以及设置在第二导电类型的第二沟槽外延层上的绝缘材料层。

公开(公告)号：US20140175540A1

公开(公告)日：2014-06-26

申请号：US13724093

申请日：2012-12-21

申请人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

发明人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

IPC分类号： H01L27/04 ,  H01L21/82

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L27/0251 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。 可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20140175536A1

公开(公告)日：2014-06-26

申请号：US13724228

申请日：2012-12-21

申请人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

发明人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/28114 ,  H01L21/3081 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0292 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。 源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。 此外，有源器件可以具有两级栅极氧化物，其中栅极氧化物的下部具有大于栅极氧化物的上部的厚度T1的厚度T2。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08680611B2

公开(公告)日：2014-03-25

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/76

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。

公开(公告)号：US08564055B2

公开(公告)日：2013-10-22

申请号：US13456406

申请日：2012-04-26

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US08519476B2

公开(公告)日：2013-08-27

申请号：US12643837

申请日：2009-12-21

申请人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/78 ,  H01L29/7811

摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

摘要翻译： 公开了自对准电荷平衡半导体器件及其形成方法。 在第一导电类型的半导体衬底上形成一个或多个平面栅极。 在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。 沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

公开(公告)号：US20130200451A1

公开(公告)日：2013-08-08

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US20130020635A1

公开(公告)日：2013-01-24

申请号：US13135985

申请日：2011-07-19

申请人： Hamza Yilmaz ,  Madhur Bobde

发明人： Hamza Yilmaz ,  Madhur Bobde

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/7803 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在重掺杂层上并具有活性电池区域和边缘终止区域的轻掺杂层。 边缘终止区域包括多个P沟道MOSFET。 通过将栅极连接到漏电极，当施加的电压等于或大于P沟道MOSFET晶体管的阈值电压Vt时，在边缘终端上形成的P沟道MOSFET晶体管顺序导通，从而优化电压 被每个地区封锁

公开(公告)号：US08343852B2

公开(公告)日：2013-01-01

申请号：US13095584

申请日：2011-04-27

申请人： Minhua Li ,  Qi Wang ,  Gordon Sim ,  Matthew Reynolds ,  Suku Kim ,  James J. Murphy ,  Hamza Yilmaz

发明人： Minhua Li ,  Qi Wang ,  Gordon Sim ,  Matthew Reynolds ,  Suku Kim ,  James J. Murphy ,  Hamza Yilmaz

IPC分类号： H01L21/00

CPC分类号： H01L21/78

摘要： A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

摘要翻译： 公开了一种从半导体结构获得单个管芯的方法。 半导体结构包括器件层，器件层又包括由预定间隔隔开的有源区。 在器件层的背侧选择性地形成厚金属，使得在有源区的背面形成厚金属，而不在预定间隔的背面形成厚金属。 然后沿着预定的间隔切割半导体结构，以将其背面的厚金属的活性区域分离成单独的管芯。

公开(公告)号：US20120319197A1

公开(公告)日：2012-12-20

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。