公开(公告)号：US07605067B2

公开(公告)日：2009-10-20

申请号：US11859618

申请日：2007-09-21

申请人： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

发明人： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

IPC分类号： H01L21/3205

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a non-volatile memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上形成隧道绝缘层，在隧道绝缘层上形成导电图案，在导电图案上形成下介电层，执行第一热处理工艺以密度较低 并且形成具有比第一经热处理的下电介质层上的下介电层的能带隙小的能带隙的中间电介质层。 该方法还包括形成上介电层，其包括与中间介电层上的下电介质层的材料基本相同的材料，执行第二热处理工艺以使中介电层和上电介质层致密并形成导电层 第二热处理的上介电层。

公开(公告)号：US08637917B2

公开(公告)日：2014-01-28

申请号：US13208640

申请日：2011-08-12

申请人： Ju-Yul Lee ,  Han-Mei Choi ,  Dong-Chul Yoo ,  Young-Jong Je ,  Ki-Hyun Hwang

发明人： Ju-Yul Lee ,  Han-Mei Choi ,  Dong-Chul Yoo ,  Young-Jong Je ,  Ki-Hyun Hwang

IPC分类号： H01L27/105

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.

摘要翻译： 绝缘图案设置在半导体衬底的表面上并且包括氮氧化硅膜。 导电图案设置在绝缘图案上。 数据存储图案和垂直沟道图案设置在垂直穿透绝缘图案和导电图案的通道孔内。 数据存储图案和垂直沟道图案沿着绝缘图案和导电图案的侧壁共形堆叠。 在与绝缘图案相邻的半导体衬底中形成凹部。 凹部相对于绝缘图案的底面凹陷。

公开(公告)号：US08497142B2

公开(公告)日：2013-07-30

申请号：US13102218

申请日：2011-05-06

申请人： Jun-Kyu Yang ,  Young-Geun Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

发明人： Jun-Kyu Yang ,  Young-Geun Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L21/02071 ,  H01L21/02074 ,  H01L21/28282 ,  H01L21/321 ,  H01L21/76834 ,  H01L22/12 ,  H01L22/20 ,  H01L27/1052 ,  H01L27/10817 ,  H01L27/10873 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2436 ,  H01L28/40 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675

摘要： Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.

摘要翻译： 形成导电图案的方法包括在基板上形成包括金属元素的导电层。 导电层被部分地蚀刻以产生包括金属元素的氧化物的残渣并且形成多个单独形成的导电层图案。 清洁气体流入包括导电层图案的基板上。 蒸发金属化合物以除去残留物中所含的金属元素，并通过一部分清洁气体和氧气的反应在导电层图案和基板的表面部分上形成绝缘界面层。 可以从导电层图案中除去残留物以抑制漏电流的产生。

公开(公告)号：US08440527B2

公开(公告)日：2013-05-14

申请号：US12659357

申请日：2010-03-05

申请人： Dong-Chul Yoo ,  Eun-Ha Lee ,  Hyung-Ik Lee ,  Ki-Hyun Hwang ,  Sung Heo ,  Han-Mei Choi ,  Yong-Koo Kyoung ,  Byong-Ju Kim

发明人： Dong-Chul Yoo ,  Eun-Ha Lee ,  Hyung-Ik Lee ,  Ki-Hyun Hwang ,  Sung Heo ,  Han-Mei Choi ,  Yong-Koo Kyoung ,  Byong-Ju Kim

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/02145 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L27/11521

摘要： A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.

摘要翻译： 提供了一种存储器件及其制造方法。 存储器件包括在衬底上的隧道电介质层，隧道电介质层上的电荷存储层，电荷存储层上的阻挡介电层，阻挡电介质层包括具有氧化硅的第一电介质层， 所述第一电介质层具有硅酸铝，以及形成在所述第二电介质层上并具有氧化铝的第三电介质层和所述阻挡电介质层上的上电极。

公开(公告)号：US20120276696A1

公开(公告)日：2012-11-01

申请号：US13456415

申请日：2012-04-26

申请人： Jun-Kyu Yang ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn ,  Han-Mei Choi ,  Dong-Chul Yoo

发明人： Jun-Kyu Yang ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn ,  Han-Mei Choi ,  Dong-Chul Yoo

IPC分类号： H01L21/336

CPC分类号： H01L29/7926 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889

摘要： A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.

摘要翻译： 一种垂直结构的非易失性存储器件，其中防止栅介质层向衬底突出; 降低了接地选择线（GSL）电极的电阻，使得非易失性存储器件高度集成并且具有改进的可靠性，并且提供了其制造方法。 该方法包括：在硅衬底上依次形成多晶硅层和绝缘层; 通过所述多晶硅层和所述绝缘层形成栅介质层和沟道层，所述栅介质层和所述沟道层在垂直于所述硅衬底的方向上延伸; 形成用于使所述硅衬底暴露于所述绝缘层和所述多晶硅层的开口; 通过在预定温度下使用含卤素反应气体去除通过开口暴露的多晶硅层; 并在通过去除多晶硅层形成的空间中填充金属层。

公开(公告)号：US20120037977A1

公开(公告)日：2012-02-16

申请号：US13208640

申请日：2011-08-12

申请人： Ju-Yul Lee ,  Han-Mei Choi ,  Dong-Chul Yoo ,  Young-Jong Je ,  Ki-Hyun Hwang

发明人： Ju-Yul Lee ,  Han-Mei Choi ,  Dong-Chul Yoo ,  Young-Jong Je ,  Ki-Hyun Hwang

IPC分类号： H01L27/105 ,  H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.

摘要翻译： 绝缘图案设置在半导体衬底的表面上并且包括氮氧化硅膜。 导电图案设置在绝缘图案上。 数据存储图案和垂直沟道图案设置在垂直穿透绝缘图案和导电图案的通道孔内。 数据存储图案和垂直沟道图案沿着绝缘图案和导电图案的侧壁共形堆叠。 在与绝缘图案相邻的半导体衬底中形成凹部。 凹部相对于绝缘图案的底面凹陷。

公开(公告)号：US20100200907A1

公开(公告)日：2010-08-12

申请号：US12704312

申请日：2010-02-11

申请人： Dong Chul Yoo ,  Eun-Ha Lee ,  Byong-Ju Kim ,  Hyung-Ik Lee ,  Sung Heo ,  Han-Mei Choi ,  Chan-Hee Park ,  Ki-Hyun Hwang

发明人： Dong Chul Yoo ,  Eun-Ha Lee ,  Byong-Ju Kim ,  Hyung-Ik Lee ,  Sung Heo ,  Han-Mei Choi ,  Chan-Hee Park ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L21/762 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L21/7605 ,  H01L21/7607 ,  H01L21/76224 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234

摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.

摘要翻译： 提供了一种半导体集成电路器件。 半导体集成电路器件包括形成在半导体衬底内并限定有源区的多个隔离区。 在每个有源区域中形成隧道层和陷阱种子层，并且依次堆叠在隔离区域之间。 陷阱层形成在捕获种子层上并且比每个隔离区的顶表面进一步突出。 在捕获层上形成阻挡层。 在阻挡层上形成栅电极。

公开(公告)号：US07560349B2

公开(公告)日：2009-07-14

申请号：US11366453

申请日：2006-03-03

申请人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

发明人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/022 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02247 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/318 ,  H01L29/513 ,  H01L29/7881

摘要： A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

公开(公告)号：US20080090353A1

公开(公告)日：2008-04-17

申请号：US11859618

申请日：2007-09-21

申请人： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

发明人： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a non-volatie memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.

摘要翻译： 制造非挥发性记忆装置的方法包括在基板上形成隧道绝缘层，在隧道绝缘层上形成导电图案，在导电图案上形成下介电层，进行第一热处理工艺以密度较低 并且形成具有比第一经热处理的下电介质层上的下介电层的能带隙小的能带隙的中间电介质层。 该方法还包括形成上介电层，其包括与中间介电层上的下电介质层的材料基本相同的材料，执行第二热处理工艺以使中介电层和上电介质层致密并形成导电层 第二热处理的上介电层。