公开(公告)号：US20050082568A1

公开(公告)日：2005-04-21

申请号：US10862452

申请日：2004-06-08

申请人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

发明人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

IPC分类号： H01L21/28 ,  H01L21/338 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

摘要翻译： 半导体器件具有蓝宝石衬底，设置在蓝宝石衬底上的由GaN制成的半导体层，设置在半导体层上的多层膜和与该多层膜欧姆接触的电极。 已经通过交替地堆叠具有不同量的极化或不同量的自发极化的两种类型的半导体层，并且每个含有n型杂质，以便在两种类型的半导体层之间的界面处诱导电子而形成多层膜。 这允许电极和多层膜之间的接触电阻和电流传输路径中的寄生电阻降低到比常规半导体器件中的值更低的值。

公开(公告)号：US20050001235A1

公开(公告)日：2005-01-06

申请号：US10834362

申请日：2004-04-29

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/338 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328 ,  H01S5/30

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电基板上并由高电阻的Al x Ga 1-x N构成的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。

公开(公告)号：US06376898B1

公开(公告)日：2002-04-23

申请号：US09631104

申请日：2000-08-01

申请人： Tomoya Uda ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara

发明人： Tomoya Uda ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara

IPC分类号： H01L2973

CPC分类号： H01L29/0692 ,  H01L27/0207 ,  H01L27/082 ,  H01L29/737

摘要： An inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit transistors, each including a base, an emitter and a collector. In the planar layout of the device, a position of a first one of the transistors is shifted from a position of a second one of the transistors in a direction in which the banks extend. The first and second transistors belong to first and second ones of the banks, respectively, which are adjacent to each other. The second transistor is closer to the first transistor than any other transistor in the second bank.

摘要翻译： 本发明的半导体集成电路器件包括在衬底上的多个晶体管组。 这些堤被布置成在设备的平面布局中彼此基本平行。 每个所述存储体包括多个单元晶体管，每个单元晶体管包括基极，发射极和集电极。 在器件的平面布局中，晶体管中的第一个晶体管的位置沿着两个晶体管延伸的方向从第二晶体管的位置移位。 第一和第二晶体管分别属于彼此相邻的第一和第二晶体管。 第二晶体管比第二组中的任何其它晶体管更靠近第一晶体管。

公开(公告)号：US06365513B1

公开(公告)日：2002-04-02

申请号：US09162232

申请日：1998-09-29

申请人： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

发明人： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

IPC分类号： H01L2166

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

摘要翻译： 在衬底中形成具有底部的通孔，然后在通孔的至少一个侧壁上形成导体层。 此后，通过去除衬底的与形成通孔的衬底的另一部分相对的部分使得导体层暴露而使衬底变薄。

公开(公告)号：US07683399B2

公开(公告)日：2010-03-23

申请号：US11758304

申请日：2007-06-05

申请人： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L31/0328

CPC分类号： H01L29/7787 ,  H01L29/045 ,  H01L29/0891 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/452

摘要： There is provided a normally-off type transistor made of a nitride semiconductor. The transistor includes; an undoped GaN layer which forms a channel region; an undoped Al0.2Ga0.8N layer which is formed on the undoped GaN layer and has a band gap larger than that of the undoped GaN layer; a p-type Al0.2Ga0.8N control layer which is formed on the undoped Al0.2Ga0.8N layer, has a p-type conductivity and forms a control region; an Ni gate electrode which contacts with the p-type Al0.2Ga0.8N control layer; a Ti/Al source electrode and a Ti/Al drain electrode which are formed beside the p-type Al0.2Ga0.8N control layer; and an Ni ohmic electrode which is connected to the undoped GaN layer and serves as a hole absorbing electrode. With this transistor, it is possible to achieve a large-current operation and a high switching speed.

摘要翻译： 提供了由氮化物半导体制成的常关型晶体管。 晶体管包括： 形成沟道区的未掺杂GaN层; 未掺杂的Al0.2Ga0.8N层，其形成在未掺杂的GaN层上，并且具有比未掺杂的GaN层的带隙大的带隙; 形成在未掺杂的Al0.2Ga0.8N层上的p型Al0.2Ga0.8N控制层具有p型导电性并形成控制区; 与p型Al0.2Ga0.8N控制层接触的Ni栅电极; 形成在p型Al0.2Ga0.8N控制层旁边的Ti / Al源电极和Ti / Al漏电极; 以及连接到未掺杂的GaN层并用作空穴吸收电极的Ni欧姆电极。 利用该晶体管，可以实现大电流动作和高切换速度。

公开(公告)号：US07439621B1

公开(公告)日：2008-10-21

申请号：US09707844

申请日：2000-11-08

申请人： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L23/34 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L27/0207 ,  H01L27/088 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

摘要： The RF device of the present invention includes: a semiconductor substrate; and first and second semiconductor components provided on the substrate. Each of the components includes source electrodes, a gate electrode and a drain electrode. And multiple through holes, which pass through the substrate in the thickness direction, are opened in a region of the substrate between the two components. To enhance the effect of suppressing electrical interference between the components, a gap between two adjacent ones of the through holes is preferably smaller than the thickness of the substrate.

摘要翻译： 本发明的RF器件包括：半导体衬底; 以及设置在基板上的第一和第二半导体部件。 每个组件包括源电极，栅电极和漏电极。 并且在两个部件之间的基板的区域中打开穿过基板的厚度方向上的多个通孔。 为了增强抑制部件之间的电气干扰的效果，两个相邻的通孔之间的间隙优选小于基板的厚度。

公开(公告)号：US07148557B2

公开(公告)日：2006-12-12

申请号：US10650702

申请日：2003-08-29

申请人： Manabu Yanagihara ,  Naohiro Tsurumi ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Manabu Yanagihara ,  Naohiro Tsurumi ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L27/082

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/42304 ,  H01L29/7371

摘要： A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

摘要翻译： 双极晶体管包括：具有本征基极区域和外部基极区域的第一半导体层; 以及第二半导体层，其具有位于本征基极区上的作为发射极区域或集电极区域的部分。 使用与第二半导体层相同的半导体材料在非本征基极区域上提供电容膜。 在第一半导体层上形成基极以覆盖电容膜和外部基极区。

公开(公告)号：US07078743B2

公开(公告)日：2006-07-18

申请号：US10834362

申请日：2004-04-29

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L31/0328

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电基板上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。

公开(公告)号：US08203376B2

公开(公告)日：2012-06-19

申请号：US12445390

申请日：2007-11-20

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H03K17/687

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

摘要翻译： 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US07456707B2

公开(公告)日：2008-11-25

申请号：US11194460

申请日：2005-08-02

申请人： Naohiro Tsurumi ,  Kazuhiro Yahata ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda ,  Atsuhiko Kanda

发明人： Naohiro Tsurumi ,  Kazuhiro Yahata ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda ,  Atsuhiko Kanda

IPC分类号： H03H9/54

CPC分类号： H03H9/173 ,  H03H3/04 ,  H03H9/172 ,  H03H9/564 ,  H03H2003/021

摘要： An acoustic resonator includes: a substrate; a resonator film which is supported above the main surface of the substrate and includes a piezoelectric film and a pair of a top electrode and a bottom electrode which are formed on part of the top surface and part of the bottom surface of the piezoelectric film, respectively, to face each other via the piezoelectric film; and a support which is formed on the main surface of the substrate to support the resonator film from below. A resonance cavity is provided in part of a region between the substrate and the resonator film below at least a portion of part of the resonator film where the top electrode and the bottom electrode coincide with each other and an isolation cavity is provided in other part of said region where the support and the resonance cavity do not exist.

摘要翻译： 声谐振器包括：基板; 一种谐振膜，其被支撑在基板的主表面上方，分别包括压电膜和一对顶电极和底电极，它们分别形成在压电膜的顶表面和底表面的一部分上 通过压电膜相互面对; 以及形成在基板的主表面上以从下方支撑谐振膜的支撑体。 谐振腔被设置在基板和谐振器膜之间的区域的一部分的下方，在谐振膜的至少一部分之上，其中顶部电极和底部电极彼此重合，并且在另一部分中设置隔离腔 所述区域不存在支撑和谐振腔。