公开(公告)号：US07003605B2

公开(公告)日：2006-02-21

申请号：US10242522

申请日：2002-09-12

申请人： David John Craft ,  Charles Ray Johns

发明人： David John Craft ,  Charles Ray Johns

IPC分类号： G06F13/42

CPC分类号： G06F13/4072

摘要： The present invention provides employing differential transitional encoding with a differential bus. Employing the differential transitional encoding comprises dividing the differential bus into one or more groups comprising four bus lines. Employment of the differential bus also comprises asserting half the bus lines of a group during a bus data transfer, thereby defining an asserted set of bus lines and a de-asserted set of bus lines. The method and system further comprises transmitting data by differentially driving two of the bus lines, one bus line per set, by de-asserting one of the bus lines of the asserted set, and asserting one of the bus lines of the de-asserted set.

摘要翻译： 本发明采用差分总线进行差分过渡编码。 使用差分过渡编码包括将差分总线划分成包括四条总线线路的一个或多个组。 差分总线的使用还包括在总线数据传输期间断言一组总线的总线，从而定义一组断言的总线和一组断言的总线线路。 该方法和系统还包括通过差分驱动两条总线线路，每组一条总线线路，通过取消断言被断言的一组总线线路，并且断言取消断言的一组总线线路来传输数据 。

公开(公告)号：US06961820B2

公开(公告)日：2005-11-01

申请号：US10366440

申请日：2003-02-12

申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/12

CPC分类号： G06F12/126

摘要： A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

摘要翻译： 提供了一种系统和方法，用于在计算机系统中用高速缓存高效地处理数据。 计算机系统具有处理器，缓存和系统存储器。 处理器发出流数据的数据请求。 流数据具有一个或多个小数据部分。 系统存储器与处理器通信。 系统存储器具有用于存储流数据的特定区域。 缓存耦合到处理器。 高速缓存具有为流数据锁定的预定义区域。 高速缓存控制器耦合到高速缓存，并且与处理器和系统存储器通信，以将流式数据的至少一个小数据部分从系统存储器的特定区域发送到高速缓存的预定义区域 在缓存的预定义区域中没有找到小数据部分。

公开(公告)号：US06820143B2

公开(公告)日：2004-11-16

申请号：US10322127

申请日：2002-12-17

申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

IPC分类号： G06F1328

CPC分类号： G06F12/0817 ,  G06F12/0897

摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

摘要翻译： 提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。 该系统包括第一和第二处理器。 第一个处理器需要数据。 该系统还包括与第一处理器通信的目录。 目录接收到数据的数据请求，并包含有关数据存储位置的信息。 缓存耦合到第二处理器。 当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。

公开(公告)号：US06628291B1

公开(公告)日：2003-09-30

申请号：US09389200

申请日：1999-09-02

申请人： Jimmie Darius Edrington ,  Charles Ray Johns ,  John Alvin Voltin ,  Dzung Q. Vu

发明人： Jimmie Darius Edrington ,  Charles Ray Johns ,  John Alvin Voltin ,  Dzung Q. Vu

IPC分类号： G09G536

CPC分类号： G09G5/397 ,  G09G5/14 ,  G09G2320/0686

摘要： A frame buffer system includes a first frame buffer containing a first set of pixels, and a second frame buffer containing a second set of pixels. A first register is connected to an output of the first frame buffer, wherein the first register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A second register is connected to an output of the second frame buffer, wherein the second register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A selection logic is connected to the first frame buffer and to the second frame buffer. The selection logic selectively selects pixels to be read from the first frame buffer and the second frame buffer into the first register and the second register. A multiplexer has a first input connected to an output of the first register, a second input connected to an output of the second register, and an output configured for connection to a digital to analog converter. The first multiplexer selectively reads the number of pixels from the first register and the second register and a portion of the group of bytes of data for each pixel.

摘要翻译： 帧缓冲器系统包括包含第一组像素的第一帧缓冲器和包含第二组像素的第二帧缓冲器。 第一寄存器连接到第一帧缓冲器的输出，其中第一寄存器存储多个像素，其中针对每个像素数存储一组数据字节。 第二寄存器连接到第二帧缓冲器的输出，其中第二寄存器存储多个像素，其中针对每个像素数存储一组数据字节。 选择逻辑连接到第一帧缓冲器和第二帧缓冲器。 选择逻辑选择性地选择要从第一帧缓冲器和第二帧缓冲器读取的像素到第一寄存器和第二寄存器。 多路复用器具有连接到第一寄存器的输出的第一输入，连接到第二寄存器的输出的第二输入和被配置为连接到数模转换器的输出。 第一复用器选择性地读取来自第一寄存器和第二寄存器的像素数量以及每个像素的数据字节组的一部分。

公开(公告)号：US5765041A

公开(公告)日：1998-06-09

申请号：US646010

申请日：1996-05-07

申请人： Cory Ansel Cherichetti ,  Paul David Dinicola ,  Charles Ray Johns ,  Omar Mahmoud Rahim ,  David Andrew Rice ,  Mark Ernest Van Nostrand

发明人： Cory Ansel Cherichetti ,  Paul David Dinicola ,  Charles Ray Johns ,  Omar Mahmoud Rahim ,  David Andrew Rice ,  Mark Ernest Van Nostrand

IPC分类号： G06F13/38 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G06F9/46 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F5/12 ,  G06F13/28 ,  G06F5/065 ,  G06F2205/064 ,  G06F2205/066 ,  G06F2205/126

摘要： Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.

摘要翻译： 使用主机存储器中的一个或多个虚拟先进先出（FIFO）寄存器和位于子系统存储器中的对应的一组虚拟FIFO，数据通过系统总线以有效的方式从主机系统传送到连接到主机的子系统 。 传输控制器控制从主机FIFO到子系统FIFO的数据传输，同时子系统处理器从子系统FIFO读取和处理数据。 通过在传送到子系统之前在主机FIFO中累积数据，与系统总线上的数据传输启动和停止相关的开销显着降低。

公开(公告)号：US09703516B2

公开(公告)日：2017-07-11

申请号：US13269583

申请日：2011-10-08

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F3/00 ,  G06F3/14 ,  G09G5/14

CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

公开(公告)号：US20120030386A1

公开(公告)日：2012-02-02

申请号：US13269583

申请日：2011-10-08

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F13/36

CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

摘要翻译： 灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。 灵活的I / O接口以特定组件确定的速率从组件接收数据。 然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。 因此，保持与各个I / O控制器的接口。 灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。 在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

公开(公告)号：US07814281B2

公开(公告)日：2010-10-12

申请号：US11468317

申请日：2006-08-30

申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichum Peter Liu ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichum Peter Liu ,  Thuong Quang Truong

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831 ,  G06F2213/0038

摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.

摘要翻译： 本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。 从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

公开(公告)号：US07721128B2

公开(公告)日：2010-05-18

申请号：US11425472

申请日：2006-06-21

申请人： Charles Ray Johns ,  Michael Fan Wang

发明人： Charles Ray Johns ,  Michael Fan Wang

IPC分类号： G06F1/32

CPC分类号： G01K3/005 ,  G01K7/015 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/126

摘要： A computer implemented method, data processing system, and processor are provided for implementation of thermal throttling logic. A sensed temperature value is received from a digital thermal sensor representing a current temperature of a unit associated with the digital thermal sensor in the integrated circuit. The sensed temperature is reported as the current temperature in a status register. The unit in the integrated circuit is throttled in response to the current temperature exceeding a first predetermined value.

摘要翻译： 提供计算机实现的方法，数据处理系统和处理器用于实现热节流逻辑。 从表示与集成电路中的数字热传感器相关联的单元的当前温度的数字热传感器接收感测的温度值。 感测到的温度被报告为状态寄存器中的当前温度。 响应于当前温度超过第一预定值，集成电路中的单元被节流。

公开(公告)号：US07689783B2

公开(公告)日：2010-03-30

申请号：US11840284

申请日：2007-08-17

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F12/06

CPC分类号： G06F12/0284 ,  G06F13/1652

摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

摘要翻译： 提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。 公共总线用于将公共存储器耦合到各种处理器。 在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。 在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。 在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。