公开(公告)号：US20100283093A1

公开(公告)日：2010-11-11

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/10 ,  H01L21/02

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US20120119302A1

公开(公告)日：2012-05-17

申请号：US12944018

申请日：2010-11-11

申请人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

发明人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

IPC分类号： H01L23/532 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/76879 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76805 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

摘要翻译： 提供一种电结构，其包括存在于半导体衬底上的电介质层和通过电介质层存在的通路开口。 在通孔开口内存在互连。 在半导体衬底中存在金属半导体合金接触。 金属半导体合金触点具有由相对于通孔开口的中心线的凸曲面限定的周长。 限定金属半导体合金触点的凸曲率的端点与通孔开口的侧壁，互连的侧壁和半导体衬底的上表面之间的界面对准。

公开(公告)号：US08629017B2

公开(公告)日：2014-01-14

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US08188528B2

公开(公告)日：2012-05-29

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US20100207179A1

公开(公告)日：2010-08-19

申请号：US12700807

申请日：2010-02-05

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/823431 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/60 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

摘要翻译： 在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。 所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。 掺杂半导体柱构成电容器的内部电极。 在半导体鳍片和半导体柱上形成介电层和导电材料层。 图案化导电材料层以形成用于电容器的外部电极和栅电极。 可以进行单侧晕圈植入。 源极和漏极区域形成在半导体鳍片中以形成存取晶体管。 源极区域电连接到电容器的内部电极。 存取晶体管和电容器共同构成DRAM单元。

公开(公告)号：US08470684B2

公开(公告)日：2013-06-25

申请号：US13106349

申请日：2011-05-12

申请人： Chengwen Pei ,  Geng Wang

发明人： Chengwen Pei ,  Geng Wang

IPC分类号： H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/2652 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10897 ,  H01L29/945

摘要： Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.

摘要翻译： 将第一导电类型的掺杂剂注入到具有第一导电类型的掺杂的半导体衬底的顶部中，以增加作为第一导电型半导体层的顶部中的掺杂剂浓度。 在其上形成具有第二导电类型的掺杂的半导体材料层，掩埋绝缘体层和顶部半导体层。 具有窄宽度的深沟槽具有在第二导电型半导体层内的底表面，其用作掩埋板。 具有较宽宽度的深沟槽被蚀刻到下面的第一导电类型层中，并且可用于形成隔离结构。 第一导电型半导体层中的附加掺杂剂提供反向掺杂以抵抗第二导电类型的掺杂剂的向下扩散以增强电隔离。

公开(公告)号：US08299573B2

公开(公告)日：2012-10-30

申请号：US12818448

申请日：2010-06-18

申请人： Chengwen Pei ,  Xi Li ,  Geng Wang

发明人： Chengwen Pei ,  Xi Li ,  Geng Wang

IPC分类号： H01L21/02

CPC分类号： H01L29/945 ,  H01L21/3065 ,  H01L27/1087 ,  H01L29/36 ,  H01L29/66181

摘要： A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.

摘要翻译： 公开了一种沟槽和制造方法。 沟槽形状是圆柱对称的，并且通过形成掺杂剂分布而形成，掺杂剂分布随掺杂剂浓度水平而单调增加，作为进入衬底的深度的函数。 然后进行掺杂剂敏感蚀刻，导致沟槽形状提供增加的表面积，但具有相对平滑的沟槽壁。

公开(公告)号：US20110309474A1

公开(公告)日：2011-12-22

申请号：US12818448

申请日：2010-06-18

申请人： Chengwen Pei ,  Xi Li ,  Geng Wang

发明人： Chengwen Pei ,  Xi Li ,  Geng Wang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L21/3065 ,  H01L27/1087 ,  H01L29/36 ,  H01L29/66181

摘要： A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.

摘要翻译： 公开了一种沟槽和制造方法。 沟槽形状是圆柱对称的，并且通过形成掺杂剂分布而形成，掺杂剂分布随掺杂剂浓度水平而单调增加，作为进入衬底的深度的函数。 然后进行掺杂剂敏感蚀刻，导致沟槽形状提供增加的表面积，但具有相对平滑的沟槽壁。

公开(公告)号：US20120286392A1

公开(公告)日：2012-11-15

申请号：US13106349

申请日：2011-05-12

申请人： Chengwen Pei ,  Geng Wang

发明人： Chengwen Pei ,  Geng Wang

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L29/66181 ,  H01L21/2652 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10897 ,  H01L29/945

摘要： Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.

摘要翻译： 将第一导电类型的掺杂剂注入到具有第一导电类型的掺杂的半导体衬底的顶部中，以增加作为第一导电型半导体层的顶部中的掺杂剂浓度。 在其上形成具有第二导电类型的掺杂的半导体材料层，掩埋绝缘体层和顶部半导体层。 具有窄宽度的深沟槽具有在第二导电型半导体层内的底表面，其用作掩埋板。 具有较宽宽度的深沟槽被蚀刻到下面的第一导电类型层中，并且可用于形成隔离结构。 第一导电型半导体层中的附加掺杂剂提供反向掺杂以抵抗第二导电类型的掺杂剂的向下扩散以增强电隔离。

公开(公告)号：US08455327B2

公开(公告)日：2013-06-04

申请号：US13198100

申请日：2011-08-04

申请人： Chengwen Pei ,  Xi Li ,  Geng Wang

发明人： Chengwen Pei ,  Xi Li ,  Geng Wang

IPC分类号： H01L21/20

CPC分类号： H01L29/0692 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.