公开(公告)号：US07401283B2

公开(公告)日：2008-07-15

申请号：US11190334

申请日：2005-07-27

申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Scott Richard Powell ,  Hau Thien Tran

发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Scott Richard Powell ,  Hau Thien Tran

IPC分类号： H03M13/00

CPC分类号： H03M13/658 ,  H03M13/1111

摘要： Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.

摘要翻译： 在LDPC码和LDPC编码调制的迭代解码期间放大接收信号的幅度度量。 通过在解码LDPC编码信号时适当地选择用于计算初始条件的度量系数值，可以在某些SNR下实现BER的显着降低。 可以根据通信系统正在操作的特定SNR来执行度量系数值的适当选择。 通过根据给定的LDPC码，调制和噪声方差调整该度量系数值，可以显着提高解码的整体性能。 收敛速度变慢，因此解码器不会进入错误的码字，解码器的输出的移动范围受到限制，使得输出不会振荡太多，最终会移动到正确的码字。

公开(公告)号：US07328398B2

公开(公告)日：2008-02-05

申请号：US11433028

申请日：2006-05-12

申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

IPC分类号： H03M13/00 ,  G06F11/00

CPC分类号： H04L1/005 ,  H04L1/0057

摘要： Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

摘要翻译： 使用min *，min **，max *或max **的低密度奇偶校验（LDPC）码解码器及其各自的反转。 首次演示了用于解码LDPC编码信号的min *处理。 另外，当执行执行使用LDPC码编码的信号的解码所需的计算时，也可以采用max *，min **或max **（及其各自的反转）。 当解码涉及从多个可能值中确定最小和/或最大值或最小和/或最大对数校正值时，可以采用这些新参数来为LDPC码提供大大改进的解码处理。 采用本文所述的最小*，最大*，最小**或最大**（及其相应的反转）解码处理，在LDPC编码信号的解码中采用的处理步骤的总数显着减少。

公开(公告)号：US07210092B1

公开(公告)日：2007-04-24

申请号：US10338376

申请日：2003-01-08

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

IPC分类号： H03M13/03

CPC分类号： H03M13/6368 ,  H03M13/258 ,  H04L1/0003 ,  H04L1/0009 ,  H04L27/0008

摘要： Symbol by symbol variable constellation type and/or mapping capable communication device. A communication device is operable to perform processing of a variable constellation signal whose constellation varies on a symbol by symbol basis. This may involve performing encoding of input to generate the variable constellation signal; alternatively or in addition to, this may involve performing decoding of a variable constellation signal as well. In doing so, this approach may involve using a single encoder and/or decoder (depending on the application). In some instances, a single device is operable to encode a first variable constellation signal (for transmission to another device) and to decode a second variable constellation signal (that has been received from another device). In addition, a method of coding (including one or both of encoding and decoding) may also operate of a variable constellation signal whose constellation varies on a symbol by symbol basis.

摘要翻译： 符号变量星座类型和/或映射能力通信设备的符号。 通信设备可操作以执行星座基于符号依次变化的可变星座信号的处理。 这可以涉及执行输入的编码以生成可变星座信号; 或者或者除此之外，这也可以涉及对可变星座信号进行解码。 在这样做时，该方法可能涉及使用单个编码器和/或解码器（取决于应用）。 在一些情况下，单个设备可操作地对第一可变星座信号（用于传输到另一设备）进行编码，并解码第二可变星座信号（已经从另一设备接收的）。 此外，编码方法（包括编码和解码中的一个或两者）也可以对其星座按符号依次变化的可变星座信号进行操作。

公开(公告)号：US07188301B1

公开(公告)日：2007-03-06

申请号：US10338571

申请日：2003-01-08

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

IPC分类号： H03M13/03

CPC分类号： H03M13/6362 ,  H03M13/258 ,  H03M13/27 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068

摘要： Parallel concatenated turbo trellis encoder structure. A dual path turbo trellis coded modulation encoder employs two interleavers and two constituent encoders and is also operable to encode symbols whose code rate may vary on a symbol by symbol basis. In addition, each of the interleavers of the parallel concatenated turbo trellis encoder structure may perform modified interleaving where input bits are treated differently depending on the order in which they are received. This interleaving may be differentiated on a bit level. In some embodiments, the implementation of the parallel concatenated turbo trellis encoder structure ensures that the output order of encoded symbols is the same as the order in which the input is received. This input may itself be in the form of bits and/or symbols. Alternatively, the parallel concatenated turbo trellis encoder structure may also support a scrambled ordering of the encoded output with respect to the input.

摘要翻译： 平行级联turbo网格编码器结构。 双路径turbo网格编码调制编码器采用两个交织器和两个构成编码器，并且还可操作地编码码率可以逐个符号依次变化的码元。 此外，并行级联turbo网格编码器结构的每个交织器可以执行修改的交织，其中根据接收它们的顺序，输入比特被不同地对待。 可以在比特级别上区分该交织。 在一些实施例中，并行级联turbo网格编码器结构的实现确保编码符号的输出顺序与接收输入的顺序相同。 该输入本身可以是比特和/或符号的形式。 或者，并行级联turbo网格编码器结构还可以支持编码输出相对于输入的加扰排序。

公开(公告)号：US07149953B2

公开(公告)日：2006-12-12

申请号：US10782142

申请日：2004-02-19

申请人： Kelly Brian Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen

发明人： Kelly Brian Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen

IPC分类号： H03M13/03 ,  G06F11/00 ,  H03M13/11 ,  H04L27/06

CPC分类号： H04L1/0058 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1131 ,  H03M13/1134 ,  H03M13/255 ,  H03M13/6583 ,  H04L1/005

摘要： Efficient LDPC code decoding with new minus operator in a finite precision radix system. A new mathematical operator is introduced and applied to the decoding of LDPC coded signals. This new operator is referred to as the min†− (min-dagger minus) operator herein. This min†− processing is appropriately applied during the updating of the edge messages with respect to the variable nodes. In a bit level decoding approach to decoding LDPC coded signals, the updating of the edge messages with respect to the bit nodes is performed using the new min†− operator. This approach provides very comparable performance to min** processing as also applied to updating of the edge messages with respect to the bit nodes and may also provide for a significant savings in hardware. Also, within finite precision radix systems, the new min†− operator provides a means by which always meaningful results may be achieved during the decoding processing.

摘要翻译： 在有限精度基数系统中使用新的减运算符进行高效LDPC码解码。 引入新的数学运算符并将其应用于LDPC编码信号的解码。 这个新操作符在这里被称为最小† - （最小匕首减号）运算符。 在边缘消息相对于可变节点的更新期间，该最小†处理被适当地应用。 在解码LDPC编码信号的位电平解码方法中，使用新的最小†运算符执行相对于比特节点的边缘消息的更新。 这种方法提供与min **处理非常可比的性能，也适用于相对于位节点的边缘消息的更新，并且还可以显着地节省硬件。 此外，在有限精度基数系统中，新的最小运算符提供了一种在解码处理期间可以实现有意义的结果的手段。

公开(公告)号：US07093187B2

公开(公告)日：2006-08-15

申请号：US10264486

申请日：2002-10-04

申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

IPC分类号： H03M13/03

CPC分类号： H04L1/005 ,  G11B20/18 ,  H03M13/1102 ,  H03M13/256 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2785 ,  H03M13/2957 ,  H03M13/4123 ,  H03M13/4161 ,  H03M13/45 ,  H04L1/0041 ,  H04L1/006 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single TTCM encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single TTCM decoder is operable to decode each of the various rates at which the data is encoded by the TTCM encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

公开(公告)号：US20050268206A1

公开(公告)日：2005-12-01

申请号：US11171568

申请日：2005-06-30

申请人： Hau Thien Tran ,  Kelly Cameron ,  Ba-Zhong Shen

发明人： Hau Thien Tran ,  Kelly Cameron ,  Ba-Zhong Shen

IPC分类号： G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  H03M13/00 ,  H03M13/11 ,  H04L27/18 ,  H04L27/34

CPC分类号： H04L27/34 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/658 ,  H04L27/18

摘要： Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**− (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†− (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

摘要翻译： 支持LDPC（低密度奇偶校验）解码器中的位节点和校验节点处理的公共电路。 提出了一种新颖的方法，其中解码器可以使用相同的电路来执行相对于位节点的边缘消息的更新，以及在解码LDPC编码信号的上下文中关于校验节点的边缘消息的更新。 此外，提出了几个非常有效的架构来执行涉及到关于校验节点的边缘消息的更新的校验节点处理。 一个实施例使用min **（min-double-star）处理结合min ** - （min-double-star-minus）处理来执行校验节点处理。 另一个实施例使用min††（最小双匕首）处理结合最小† - （最小匕首 - 减号）处理来执行校验节点处理。 此外，可以实现单个FIFO以在并行解码实现中服务多个宏块。

公开(公告)号：US08964895B2

公开(公告)日：2015-02-24

申请号：US13245362

申请日：2011-09-26

申请人： Christopher J. Hansen ,  Jason A. Trachewsky ,  Nambirajan Seshadri ,  Kelly Brian Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen

发明人： Christopher J. Hansen ,  Jason A. Trachewsky ,  Nambirajan Seshadri ,  Kelly Brian Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen

IPC分类号： H04L27/36 ,  H04L1/00 ,  H04L1/06 ,  H04L25/03 ,  H04L27/26

CPC分类号： H04W4/18 ,  H04L1/0057 ,  H04L1/0059 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/0618 ,  H04L25/03866 ,  H04L27/2601 ,  H04W84/12 ,  H04W88/10

摘要： A wireless local area network (WLAN) transmitter includes a baseband processing module and a plurality of radio frequency (RF) transmitters. The processing module selects one of a plurality of modes of operation based on a mode selection signal. The processing module determines a number of transmit streams based on the mode selection signal. The processing of the data further continues by converting encoded data into streams of symbols in accordance with the number of transmit streams and the mode selection signal. A number of the plurality of RF transmitters are enabled based on the mode selection signal to convert a corresponding one of the streams of symbols into a corresponding RF signal such that a corresponding number of RF signals is produced.

摘要翻译： 无线局域网（WLAN）发射机包括基带处理模块和多个射频（RF）发射机。 处理模块基于模式选择信号选择多种操作模式中的一种。 处理模块基于模式选择信号确定多个发送流。 根据发送流的数量和模式选择信号，将编码数据转换为符号流，继续处理数据。 基于模式选择信号启用多个RF发射机的数量，以将符号流中的相应一个码流转换为对应的RF信号，从而产生相应数量的RF信号。

公开(公告)号：US20130166987A1

公开(公告)日：2013-06-27

申请号：US13753579

申请日：2013-01-30

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

IPC分类号： H03M13/13

CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

公开(公告)号：US08327221B2

公开(公告)日：2012-12-04

申请号：US13549577

申请日：2012-07-16

申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/1162 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/616 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583

摘要： Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

摘要翻译： 重叠的基于子矩阵的LDPC（低密度奇偶校验）解码器。 提出了新的解码方法，通过该方法，立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息，而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息，而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比，使用这种方法，在给定时间段内可以执行两倍的解码迭代，然后更新整个LDPC矩阵的所有位边消息，以及 所以。 当结合最小和处理执行这种重叠方法时，也可以节省大量的内存。