公开(公告)号：US20100167477A1

公开(公告)日：2010-07-01

申请号：US12719153

申请日：2010-03-08

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/2686 ,  H01L21/7621 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878

摘要： Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

摘要翻译： 公开了半导体结构的实施方案和形成具有选择性调节的反射率和吸收特性的结构的方法，以便在快速热退火期间选择性地控制温度变化，从而选择性地控制器件性能的变化和/或选择性地优化 这种装置的退火温度。 在快速热退火期间选择性地控制不同器件的温度变化是通过选择性地改变浅沟槽隔离结构的不同部分中的隔离材料厚度来实现的。 或者，通过选择性地改变半导体晶片的不同部分中的填充结构的图案来实现，使得不同部分中的预定量的浅沟槽隔离区域被暴露。

公开(公告)号：US20100156526A1

公开(公告)日：2010-06-24

申请号：US12342527

申请日：2008-12-23

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC分类号： H03H11/00 ,  H01L21/761 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/84

摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.

摘要翻译： 具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。 至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。 掺杂接触区域被偏置在处于或接近RF开关中的峰值电压处的电压，其移除感应电荷层内的少数电荷载流子。 少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。 诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。 还提供了用于半导体结构的设计结构。

公开(公告)号：US07736053B2

公开(公告)日：2010-06-15

申请号：US12348974

申请日：2009-01-06

申请人： William F. Clark, Jr. ,  Edward J. Nowak

发明人： William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： G01K3/06 ,  G01K7/00 ,  G01K15/00 ,  G01K17/00

CPC分类号： G01K7/015 ,  G01K7/22 ,  G01K15/00

摘要： Disclosed are embodiments of an improved on-chip temperature sensing circuit, based on bolometry, which provides self calibration of the on-chip temperature sensors for ideality and an associated method of sensing temperature at a specific on-chip location. The circuit comprises a temperature sensor, an identical reference sensor with a thermally coupled heater and a comparator. The comparator is adapted to receive and compare the outputs from both the temperature and reference sensors and to drive the heater with current until the outputs match. Based on the current forced into the heater, the temperature rise of the reference sensor can be calculated, which in this state, is equal to that of the temperature sensor.

摘要翻译： 公开了一种改进的片上温度感测电路的实施例，其基于速率测量，其提供用于理想的片上温度传感器的自校准以及在特定片上位置处感测温度的相关联的方法。 该电路包括温度传感器，具有热耦合加热器的相同参考传感器和比较器。 比较器适用于接收和比较来自温度和参考传感器的输出，并用电流驱动加热器直到输出匹配。 基于被迫进入加热器的电流，可以计算参考传感器的温度上升，在该状态下，其温度上升等于温度传感器的温升。

公开(公告)号：US07709892B2

公开(公告)日：2010-05-04

申请号：US11426698

申请日：2006-06-27

申请人： Brent A. Anderson ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Brent A. Anderson ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L29/94 ,  H01L27/88

CPC分类号： H01L21/02595 ,  H01L21/02667 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/785

摘要： A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

摘要翻译： 在传统的SOI或体衬底硅器件上提供独立半导体层的方法包括在单晶基底结构上形成非晶或多晶心轴。 然后在心轴和基底结构上形成共形多晶半导体层，其中多晶层接触基底结构。 然后将多晶半导体层重结晶，使其具有与基础结构基本相似的结晶度。 因此，以高度控制其厚度和高度的方式形成独立的半导体层并保持厚度的均匀性。

公开(公告)号：US20100047972A1

公开(公告)日：2010-02-25

申请号：US12610563

申请日：2009-11-02

申请人： William F. Clark, JR. ,  Edward J. Nowak

发明人： William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/861 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6609 ,  H01L29/772 ,  H01L29/78648

摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.

摘要翻译： 公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。 场屏蔽被夹在晶片上的上隔离层和下隔离层之间。 局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。 进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。 因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。 该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。

公开(公告)号：US07667527B2

公开(公告)日：2010-02-23

申请号：US11561480

申请日：2006-11-20

申请人： William F. Clark, Jr. ,  Edward J. Nowak

发明人： William F. Clark, Jr. ,  Edward J. Nowak

IPC分类号： H03K3/01

CPC分类号： G05F3/205

摘要： Structure and process for compensating threshold voltage variation due to process variation. The structure includes a circuit segmented into sub-blocks having a predetermined size corresponding to a characteristic length associated with a process variation. A local circuit is located in each circuit sub-block, and a reference signal coupled to each local circuit. The local circuit generates a compensation signal in response to the reference signal to adjust an electrical parameter of the respective sub-block to a predetermined value.

摘要翻译： 用于补偿由于过程变化引起的阈值电压变化的结构和过程。 该结构包括分割成具有对应于与过程变化相关联的特征长度的预定尺寸的子块的电路。 本地电路位于每个电路子块中，并且参考信号耦合到每个本地电路。 本地电路响应于参考信号产生补偿信号，以将相应子块的电参数调整到预定值。

公开(公告)号：US20100039853A1

公开(公告)日：2010-02-18

申请号：US12190040

申请日：2008-08-12

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： G11C11/00 ,  G06F17/50

CPC分类号： G11C11/412

摘要： A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; applying a voltage through asymmetric pull-up pFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; and applying a voltage through asymmetrical pass gates which provide low leakage SOI logic.

摘要翻译： 提供了使用和/或制造具有非对称结工程SRAM通孔的结构的设计结构，结构和方法。 该方法包括通过非对称下拉nFET施加电压，其具有从其主体到其源极的高结泄漏以及从主体到其漏极的低结漏; 通过非对称上拉pFET施加电压，其具有从其主体到其源极的高结泄漏以及从主体到其漏极的低结漏; 并通过提供低泄漏SOI逻辑的非对称通孔施加电压。

公开(公告)号：US20100038720A1

公开(公告)日：2010-02-18

申请号：US12192517

申请日：2008-08-15

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L27/092 ,  G06F17/50

CPC分类号： H01L29/4983 ,  H01L21/28097 ,  H01L21/28105 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

摘要： A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The multi-work function metal gate structure comprises a first type of metal with a first work function in a central region and a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function.

摘要翻译： 为双金属栅极Vt卷起结构（例如多功能金属栅极）提供了一种结构，设计结构和制造方法。 多功能金属栅极结构包括在中心区域具有第一功函数的第一类金属和在邻近中心区域的至少一个边缘区域中具有第二功函数的第二类金属。 第一个功能与第二个功能不同。

公开(公告)号：US07659579B2

公开(公告)日：2010-02-09

申请号：US11539288

申请日：2006-10-06

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L29/78

CPC分类号： H01L29/78612 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78648

摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.

摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。 因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。 还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。 该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

公开(公告)号：US07649243B2

公开(公告)日：2010-01-19

申请号：US11556833

申请日：2006-11-06

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

摘要翻译： 半导体结构包括位于隔离衬底上的半导体台面。 半导体台面包括第一端，该第一端包括通过插入其间的隔离区域与第二掺杂区域分离的第一掺杂区域。 第一掺杂区域和第二掺杂区域具有不同的极性。 半导体结构还包括位于第二掺杂区域上的半导体台面的水平表面上的沟道阻挡介电层。 半导体结构还包括使用第一端的侧壁和顶表面作为沟道区的第一器件，以及使用侧壁而不是第二端的顶表面作为沟道定位的第二器件。 相关方法源于上述半导体结构。 还包括包括半导体结构的半导体电路。