摘要:
A display device uses the load capacitances of two signal lines to perform DA conversion. Serial digital/analog conversion circuits (SDAC) in a data driver are provided for every two adjacent signal lines and use the load capacitances of these two signal lines to successively convert to analog data those data from the parallel/serial conversion circuits (PSC), PSC that correspond to the pixels of odd-numbered pixel columns and apply the converted analog data to the pixels of odd-numbered pixel columns, and successively apply data from PSC that correspond to the pixels of even-numbered pixel columns to the pixels of even-numbered pixel columns. Because the source of error of the SDAC is determined only by the difference between the two load capacitances, a polysilicon liquid crystal display device may be and the characteristics of the TFT may consequently show fluctuation, but will not act as an error source.
摘要:
Disclosed is an active matrix liquid crystal display device, comprising: a pixel matrix; a data driver circuit for driving data lines; and gate driver circuits for driving gate lines. These constituting elements are all manufactured on the same substrate, and the data driver circuit and the gate driver circuits are formed outside a sealing region located outside the pixel matrix. In this case, all data lines formed between the data driver circuit and the pixel matrix are substantially covered by at least one metal layer which is composed of a metal different from that of the data lines, wherein the metal layer is adapted to perform both light shielding and reduction of electrostatic coupling capacitance between the data lines. Thus, it is possible to improve image quality by reducing noise generated following voltage fluctuation between data lines without providing any new metal layers for shielding.
摘要:
A drive circuit for a LCD device has a plurality of drive sections corresponding to a plurality of data lines in a pixel matrix. Each drive section receives a corresponding portion of a video signal to deliver the signal portion to a corresponding data line. The output circuit of each drive section includes an nMOS transistor, first switch, second switch and a pMOS transistor connected in series between power source lines to output the signal portion through the output node connecting the first switch and the second switch together. The nMOS transistor and pMOS transistor operate alternately for delivering a a positive signal and negative signal, respectively, thereby making it unnecessary to reset the data line for reducing power dissipation.