公开(公告)号：US4958222A

公开(公告)日：1990-09-18

申请号：US363759

申请日：1989-06-09

申请人： Hiroshi Takakura ,  Tetsuya Iida ,  Junkei Goto

发明人： Hiroshi Takakura ,  Tetsuya Iida ,  Junkei Goto

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/40

CPC分类号： H01L23/5286 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5226 ,  H01L27/0203 ,  H01L2924/0002

摘要： A signal interference prevention wiring is disposed between two wirings which are arranged in parallel for transmitting a signal, and the signal interference prevention wiring is held at a constant potential.

公开(公告)号：US4908712A

公开(公告)日：1990-03-13

申请号：US320556

申请日：1989-03-08

申请人： Tadamitsu Uchiyama ,  Tetsuya Iida

发明人： Tadamitsu Uchiyama ,  Tetsuya Iida

IPC分类号： B41J2/21 ,  B41J2/205 ,  B41M1/18 ,  G03F3/08 ,  H04N1/23 ,  H04N1/46 ,  H04N1/48 ,  H04N1/52 ,  H04N1/60

CPC分类号： H04N1/6022 ,  B41M1/18

摘要： A method for reproduction of a multi-tone color image by combination of chromatic inks of cyan, magenta and yellow together with an achromatic ink of black. In the region of lower tone levels than a prescribed value, the image is formed by the complete under color removal, namely, by the sole use of the achromatic ink. In the region of higher tone levels than the prescribed value, the reproduction of the image is attained by performing the under color removal at a ratio of decrease relative to the rise of the tone levels, namely by causing the chromatic inks to overlap the achromatic ink.

摘要翻译： 通过将青色，品红色和黄色的彩色墨水与黑色的无色墨水组合在一起再现多色彩图像的方法。 在比规定值低的色调级别的区域中，通过完全的颜色除去形成图像，即通过唯一使用无色墨水来形成图像。 在比指定值高的色调级别的区域中，通过以相对于色调级别的上升的减小的比例执行色差去除，即通过使彩色墨水与无色墨水重叠来获得图像的再现 。

公开(公告)号：US4908624A

公开(公告)日：1990-03-13

申请号：US216046

申请日：1988-07-07

申请人： Junkei Goto ,  Tetsuya Iida

发明人： Junkei Goto ,  Tetsuya Iida

IPC分类号： H03M1/38 ,  H03M1/00

CPC分类号： H03M1/06 ,  H03M1/468

摘要： A successive approximation type A/D converter of the present invention has a capacitor having a predetermined capacitance value and arranged between an input terminal of a voltage comparator and a fixed potential terminal having a predetermined potential. According to the successive approximation type A/D converter of the present invention, the capacitor arranged between the input terminal of the voltage comparator and the fixed potential terminal having the predetermined potential prevents a potential at the input node of the voltage comparator from being greatly changed to exceed a power source voltage range due the influences of a local D/A converter when the sample mode is switched to the approximation mode. Therefore, the leakage of charges stored in the input side of the voltage comparator can be prevented. Accordingly, even if the amplitude of an analog input voltage is equal to the amplitude of the power source voltage, high-precision A/D conversion can still be performed.

公开(公告)号：US4845383A

公开(公告)日：1989-07-04

申请号：US480002

申请日：1983-03-29

申请人： Tetsuya Iida

发明人： Tetsuya Iida

IPC分类号： H03M1/38 ,  G01R19/00 ,  G01R19/10 ,  H03K5/08 ,  H03K5/24

CPC分类号： G01R19/0038 ,  G01R19/10 ,  H03K5/24 ,  H03K5/249

摘要： A voltage comparator circuit that is useful in A/D converters and D/A converters. The circuit comprises a comparison capacitor, a holding capacitor and input switching transistors. The holding capacitor holds the comparison voltage applied to it from the input switching transistors through the comparison capacitor. Therefore, the circuit can perform accurate voltage comparison even if the input voltages are sampled at a high sampling frequency.

摘要翻译： A / D转换器和D / A转换器有用的电压比较器电路。 电路包括比较电容器，保持电容器和输入开关晶体管。 保持电容器通过比较电容器保持从输入开关晶体管施加到其上的比较电压。 因此，即使以高采样频率对输入电压进行采样，电路也可进行精确的电压比较。

公开(公告)号：US4827260A

公开(公告)日：1989-05-02

申请号：US162264

申请日：1988-02-29

申请人： Naoki Sugawa ,  Tetsuya Iida

发明人： Naoki Sugawa ,  Tetsuya Iida

IPC分类号： H03M1/74 ,  H03M1/00 ,  H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A digital-to-analog converter of current segment type, having a plurality of first variable current sources and a second variable current source of the same structure as the first variable current sources. The converter further comprises a comparator. The comparator compares a voltage corresponding to the output current of the second variable current source with a reference voltage. The difference between these compared voltages is used to determine the output currents of the first variable current sources.

公开(公告)号：US4301427A

公开(公告)日：1981-11-17

申请号：US129737

申请日：1980-03-12

申请人： Yasoji Suzuki ,  Tetsuya Iida

发明人： Yasoji Suzuki ,  Tetsuya Iida

IPC分类号： H03K3/354 ,  H03K4/501

CPC分类号： H03K3/354 ,  H03K4/501

摘要： A Schmitt trigger astable multivibrator circuit includes a first inverter, a second inverter whose input terminal is connected to the output terminal of the first inverter, a third inverter which is constituted by a first P-channel transistor and a first N-channel transistor serially connected and whose input and output terminals are respectively connected to the output and input terminals of the second inverter. The Schmitt trigger astable multivibrator circuit further includes a second P-channel transistor connected between a positive power supply terminal and the first P-channel transistor, and a second N-channel transistor connected between a ground terminal and the first N-channel transistor, and an input signal supplied to the first inverter is also applied to the gates of the second P-channel and N-channel transistors. The astable multivibrator also includes a time constant circuit, activated in response to the second inverter's output, which connects to the first inverter's input.

摘要翻译： 施密特触发器非稳态多谐振荡器电路包括第一反相器，其输入端连接到第一反相器的输出端的第二反相器，由第一P沟道晶体管和第一N沟道晶体管串联连接的第三反相器 并且其输入和输出端分别连接到第二反相器的输出端和输入端。 施密特触发器非稳态多谐振荡器电路还包括连接在正电源端子和第一P沟道晶体管之间的第二P沟道晶体管，以及连接在接地端子和第一N沟道晶体管之间的第二N沟道晶体管，以及 提供给第一反相器的输入信号也被施加到第二P沟道和N沟道晶体管的栅极。 不稳定的多谐振荡器还包括响应于第二反相器输出而被激活的时间常数电路，其连接到第一反相器的输入端。

公开(公告)号：US4268761A

公开(公告)日：1981-05-19

申请号：US16565

申请日：1979-03-01

申请人： Yasoji Suzuki ,  Tetsuya Iida

发明人： Yasoji Suzuki ,  Tetsuya Iida

IPC分类号： H03K5/02 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018528 ,  H03K5/023

摘要： An input terminal of an interface circuit is connected to a first logic circuit which produces a first logic signal. The interface circuit compares the first logic signal with a reference voltage whose level is set between a high level and a low level of the first logic signal. The interface circuit converts levels of the signal compared. An output terminal of the interface circuit is connected to a second logic circuit whose signal levels are different from levels of the first logic signal and which is driven by the output signal compared and amplified.

摘要翻译： 接口电路的输入端连接到产生第一逻辑信号的第一逻辑电路。 接口电路将第一逻辑信号与其电平设置在第一逻辑信号的高电平和低电平之间的参考电压进行比较。 接口电路转换信号的电平进行比较。 接口电路的输出端子连接到第二逻辑电路，其信号电平与第一逻辑信号的电平不同，并且被比较和放大的输出信号驱动。

公开(公告)号：US4259686A

公开(公告)日：1981-03-31

申请号：US947432

申请日：1978-10-02

申请人： Yasoji Suzuki ,  Tetsuya Iida

发明人： Yasoji Suzuki ,  Tetsuya Iida

IPC分类号： H02J1/00 ,  G05F3/24 ,  H02M3/07 ,  H03K5/003 ,  H03K5/00

CPC分类号： H03K5/003 ,  H02M3/07

摘要： An inverter is controlled by first clock pulses for converting a positive power supply into second clock pulses having a first voltage level of the power supply and a second voltage level of a reference voltage. The second clock pulses are supplied to a capacitor. The source-drain path of a first impedance varying P-FET is connected between the output terminal of the capacitor and the reference voltage and is controlled so as to take a low impedance when the second clock pulses are at the first voltage level while a high impedance when the second clock pulses are at the second voltage level. The source-drain path of a second impedance varying P-FET is connected between the output terminal and a terminal for taking out a polarity-reversed voltage. The second impedance varying P-FET is supplied at the gate with the first clock pulses so as to be controlled to take a high impendance when the second clock pulses are at the first voltage level and a low impedance when the second clock pulses are at the second level.

摘要翻译： 逆变器由第一时钟脉冲控制，用于将正电源转换成具有电源的第一电压电平和参考电压的第二电压电平的第二时钟脉冲。 第二个时钟脉冲被提供给电容器。 第一阻抗变化P-FET的源极 - 漏极路径被连接在电容器的输出端子和参考电压之间，并且当第二时钟脉冲处于第一电压电平时被控制成低阻抗，而高 当第二时钟脉冲处于第二电压电平时的阻抗。 第二阻抗变化P-FET的源极 - 漏极路径连接在输出端子和用于取出极性反转电压的端子之间。 第二阻抗变化P-FET在栅极处以第一时钟脉冲提供，以便当第二时钟脉冲处于第一电压电平时被控制以产生高阻抗，而当第二时钟脉冲处于第二时钟脉冲时 二级

公开(公告)号：US08835443B2

公开(公告)日：2014-09-16

申请号：US12626443

申请日：2009-11-25

申请人： Hisashi Kawasaki ,  Hiroyuki Abe ,  Kazuhide Hayakawa ,  Tetsuya Iida ,  Shinichi Kikuchi ,  Takayuki Yamaguchi ,  Toyomichi Nanayama ,  Hironori Kurachi ,  Masahiro Tamaru ,  Yoshikazu Hori ,  Mitsuru Takahashi ,  Takayuki Yoshida ,  Toshiyuki Sakai

发明人： Hisashi Kawasaki ,  Hiroyuki Abe ,  Kazuhide Hayakawa ,  Tetsuya Iida ,  Shinichi Kikuchi ,  Takayuki Yamaguchi ,  Toyomichi Nanayama ,  Hironori Kurachi ,  Masahiro Tamaru ,  Yoshikazu Hori ,  Mitsuru Takahashi ,  Takayuki Yoshida ,  Toshiyuki Sakai

IPC分类号： A61K31/519 ,  C07D239/545 ,  C07D471/04 ,  C07D487/04

CPC分类号： C07D471/04 ,  A61K31/519 ,  C07C275/30 ,  C07C275/50 ,  C07C2601/16 ,  C07D239/545 ,  C07D239/553 ,  C07D239/62 ,  C07D471/16 ,  C07D487/04 ,  C07F9/53

摘要： The present invention relates to a pyrimidine compound or a pharmaceutically acceptable salt thereof represented by the following formula [I] wherein each symbol is as defined in the specification and a method of therapeutically or prophylactically treating an undesirable cell proliferation, comprising administering such a compound. The compound of the present invention has superior activity in suppressing undesirable cell proliferation, particularly, an antitumor activity, and is useful as an antitumor agent for the prophylaxis or treatment of cancer, rheumatism, and the like. In addition, the compound of the present invention can be a more effective antitumor agent when used in combination with other antitumor agents such as an alkylating agent or metabolism antagonist.

摘要翻译： 本发明涉及由下式[I]表示的嘧啶化合物或其药学上可接受的盐，其中每个符号如说明书中所定义，以及治疗或预防性治疗不期望的细胞增殖的方法，包括施用这种化合物。 本发明的化合物在抑制不期望的细胞增殖，特别是抗肿瘤活性方面具有优异的活性，可用作预防或治疗癌症，风湿病等的抗肿瘤剂。 此外，当与其它抗肿瘤剂如烷化剂或代谢拮抗剂组合使用时，本发明的化合物可以是更有效的抗肿瘤剂。

公开(公告)号：US08669610B2

公开(公告)日：2014-03-11

申请号：US13646079

申请日：2012-10-05

申请人： Hideyuki Ono ,  Tetsuya Iida

发明人： Hideyuki Ono ,  Tetsuya Iida

IPC分类号： H01L29/68

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/66121 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/861 ,  H01L29/8611 ,  H03F1/523 ,  H03F3/195 ,  H03F2200/444

摘要： A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 μm or more.

摘要翻译： 一种高频功率放大器，其类型安装在具有高频功率场效应晶体管和栅极保护二极管的手机的RF模块中，高频功率场效应晶体管和栅极保护二极管耦合在高频功率场效应晶体管的栅极和源极之间。 栅极保护二极管具有形成在p型外延层的主表面上的n型区域，形成在n型区域的主表面中心的第一p型区域，形成在n型区域的主表面上的第二p型区域 从n型区域的主表面周围的n型区域周围的外延层和用于将第二p型区域耦合到衬底本体的p +型掩埋层。 p +型掩埋层和n +型区域的端部之间的距离为7μm以上。