Method for making a thin film magnetic head having a protective coating
    61.
    发明授权
    Method for making a thin film magnetic head having a protective coating 失效
    制造具有保护涂层的薄膜磁头的方法

    公开(公告)号:US5271802A

    公开(公告)日:1993-12-21

    申请号:US987509

    申请日:1992-12-07

    IPC分类号: G11B5/31 G11B5/60 G11B5/71

    摘要: A method for making a magnetic head slider having a protective coating on the rails thereof, the protective coating containing a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.

    摘要翻译: 一种用于制造在其轨道上具有保护涂层的磁头滑块的方法,所述保护涂层包含薄粘合层,非晶氢化碳薄层和薄掩蔽层。 在将薄膜磁头研磨成选定的尺寸之后,但是在空气轴承表面上产生轨道图案之前,保护涂层沉积在滑块的空气支承表面上。 保护涂层在轨道制造过程中保护磁头,并且在磁记录系统中使用可保护磁头免受磨损和腐蚀的损害。

    Self-aligned process for providing an improved high performance bipolar
transistor
    62.
    发明授权
    Self-aligned process for providing an improved high performance bipolar transistor 失效
    用于提供改进的高性能双极晶体管的自对准工艺

    公开(公告)号:UST104803I4

    公开(公告)日:1984-11-06

    申请号:US580962

    申请日:1984-02-16

    申请人: Cheng T. Horng

    发明人: Cheng T. Horng

    IPC分类号: H01L29/732

    CPC分类号: H01L29/7325

    摘要: A bipolar transistor structure formed in a monolithic silicon semiconductor substrate of p type having a planar surface comprising: a subcollector of n type formed in the substrate; an epitaxial layer of n type formed on said planar surface of said substrate and also having a planar surface, the epitaxial layer having a thickness in the order of 1.0 to 1.5 micrometers; an enclosed deep recessed oxide isolation trench enclosing a transistor structure area of the substrate and the epitaxial layer, the enclosed deep recessed oxide isolation trench having a depth extending from said planar surface of said epitaxial layer through the subcollector region; a shallow recessed oxide isolation trench, the relatively shallow recessed oxide isolation trench being wholly enclosed by the deep recessed oxide isolation trench and intersecting the deep recessed oxide isolation trench at two spaced apart points to divide said transistor structure area enclosed by the deep recessed oxide isolation trench into first and second areas, the first and second areas being electrically connected one to the other by the subcollector region;a shallow depth emitter region formed in a limited portion of the first area of said epitaxial layer, the emitter region having a depth in the order of 0.1 micrometers;an active base region formed beneath said emitter region in the limited portion the first area of said epitaxial layer, the active base region having a width in the order of 0.1 micrometers;an inactive base region surrounding the emitter region and active base region, the inactive base region being wholly contained within the first area of said epitaxial layer;an emitter-base junction contained within said first area of the epitaxial layer and extending to the surface of the epitaxial layer;a composite layer of silicon dioxide and silicon nitride having a width of approximately 0.2 to 0.3 micrometers, the composite layer being positioned on the planar surface of the epitaxial layer over the surface juncture of said emitter-base junction, the silicon dioxide having a thickness of approximately 500.ANG. and the silicon nitride layer having a thickness of approximately 500.ANG.;the second area of the epitaxial layer containing a collector reach through, the shallow recessed oxide isolation trench isolating the collector reach through from the inactive base region;a layer of polysilicon p type on said planar surface of the epitaxial layer and in physical and electrical contact with the inactive base region, the polysilicon layer extending over a portion of said enclosed relatively deep recessed oxide isolation trench; and,a base contact physically and electrically contacting the portion of the polysilicon layer which extends over the enclosed deep recessed oxide isolation trench.

    Bipolar transistor
    63.
    发明授权
    Bipolar transistor 失效
    双极晶体管

    公开(公告)号:US4392149A

    公开(公告)日:1983-07-05

    申请号:US273705

    申请日:1981-06-15

    摘要: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

    摘要翻译: 公开了一种用于提供改进的双极晶体管结构的自对准工艺。 该方法包括中间绝缘层的化学蚀刻,以在自对准发射极工艺中切割出不同绝缘材料的另一顶层,其中发射极接触与多晶硅基底接触的间隔减小到约0.2至0.3的量级 微米。 此外,在该过程中,形成发射极插塞以阻挡来自外部基极的重P +离子剂量植入物的发射极区域。

    Magnetic tunnel junction (MTJ) to reduce spin transfer magnetization switching current
    65.
    发明授权
    Magnetic tunnel junction (MTJ) to reduce spin transfer magnetization switching current 有权
    磁隧道结(MTJ)降低自旋转移磁化开关电流

    公开(公告)号:US08456893B2

    公开(公告)日:2013-06-04

    申请号:US12584971

    申请日:2009-09-15

    IPC分类号: G11C11/00

    CPC分类号: H01L43/08 H01L43/12

    摘要: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to

    摘要翻译: 公开了将旋转RAM中的自旋转移磁化开关电流(Jc)最小化为<1×106A / cm 2的MTJ。 MTJ具有Co60Fe20B20 / MgO / Co60Fe20B20配置,其中CoFeB AP1钉扎和自由层是无定形的,并且通过ROX或NOX工艺形成结晶MgO隧道势垒。 覆盖层优选为Hf / Ru复合材料,其中下部Hf层用作优异的吸氧材料,以减少自由层/覆盖层界面处的磁性“死层”,从而增加dR / R,并降低He和Jc 。 退火温度降低至约280℃,以产生比350℃退火更平滑的CoFeB / MgO界面和较小的偏移场。 在第二实施例中,AP1层具有CoFeB / CoFe构型,其中下CoFeB层是非晶的,并且上CoFe层是结晶的,以进一步提高dR / R,并将RA降低到10欧姆/ m 2。

    High performance MTJ elements for STT-RAM and method for making the same
    66.
    发明授权
    High performance MTJ elements for STT-RAM and method for making the same 有权
    用于STT-RAM的高性能MTJ元件和制作相同的方法

    公开(公告)号:US08436437B2

    公开(公告)日:2013-05-07

    申请号:US12803191

    申请日:2010-06-21

    IPC分类号: H01L29/82

    摘要: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness or an amorphous ferromagnetic layer of Co40Fe40B20 of approximately 15 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

    摘要翻译: 利用自旋角度动量的转移作为改变自由层的磁矩方向的机构的STT-MTJ MRAM单元包括IrMn钉扎层,SyAP钉扎层,自然氧化的结晶的MgO隧穿势垒层,其形成于 被钉扎层的Ar离子等离子体平滑表面和包含大约20埃厚度的Co60Fe20B20的非晶层的自由层或者在3和6的Fe的两个结晶层之间形成约15埃厚度的Co40Fe40B20的非晶铁磁层 埃厚度。 自由层的特征在于低吉尔伯特阻尼因子和对传导电子的非常强的偏振作用。 所得到的电池具有低临界电流,高dR / R,并且多个这样的电池将呈现电阻和钉扎层磁化角分散的低变化。

    Magnetic tunnel junction (MTJ) to reduce spin transfer magnetizaton switching current
    68.
    发明授权
    Magnetic tunnel junction (MTJ) to reduce spin transfer magnetizaton switching current 有权
    磁隧道结(MTJ)降低自旋转移磁化开关电流

    公开(公告)号:US08269292B2

    公开(公告)日:2012-09-18

    申请号:US12584946

    申请日:2009-09-15

    CPC分类号: H01L43/08 H01L43/12

    摘要: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to

    摘要翻译: 公开了将旋转RAM中的自旋转移磁化开关电流(Jc)最小化为<1×106A / cm 2的MTJ。 MTJ具有Co60Fe20B20 / MgO / Co60Fe20B20配置,其中CoFeB AP1钉扎和自由层是无定形的,并且通过ROX或NOX工艺形成结晶MgO隧道势垒。 覆盖层优选为Hf / Ru复合材料,其中下部Hf层用作优异的吸氧材料,以减少自由层/覆盖层界面处的磁性“死层”,从而增加dR / R,并降低He和Jc 。 退火温度降低至约280℃,以产生比350℃退火更平滑的CoFeB / MgO界面和较小的偏移场。 在第二实施例中,AP1层具有CoFeB / CoFe构型,其中下CoFeB层是非晶的,并且上CoFe层是结晶的,以进一步改善dR / R,并将较低的RA降低至10nhm /μm2。

    Structure and method to fabricate high performance MTJ devices for spin-transfer torque (STT)-RAM
    69.
    发明授权
    Structure and method to fabricate high performance MTJ devices for spin-transfer torque (STT)-RAM 有权
    用于制造自旋转矩(STT)-RAM的高性能MTJ装置的结构和方法

    公开(公告)号:US08138561B2

    公开(公告)日:2012-03-20

    申请号:US12284066

    申请日:2008-09-18

    IPC分类号: H01L29/82

    摘要: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by a NOX process, a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0, and a Ru capping layer to enhance the spin scattering effect and increase dR/R. Good write margin is achieved by modifying the NOX process to afford a RA less than 10 ohm-μm2 and good read margin is realized with a dR/R of >100% by annealing at 330° C. or higher to form crystalline CoFeB free layers. The NCC thickness is maintained in the 6 to 10 Angstrom range to reduce Rp and avoid Fe(Si) granules from not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A FeSiO layer may be inserted below the Ru layer in the capping layer to prevent the Ru from causing a high damping constant in the upper CoFeB free layer.

    摘要翻译: 公开了一种STT-RAM MTJ,其具有通过NOX工艺形成的MgO隧道势垒,具有中间纳米通道层的CoFeB / FeSiO / CoFeB复合自由层以最小化Jc0,以及Ru覆盖层以增强自旋散射效应并增加 dR / R。 通过改变NOX工艺以获得RA小于10欧姆 - μm2的良好的写入余量,并且通过在330℃或更高温度退火以dO / R> 100%实现良好的读取余量以形成结晶CoFeB自由层 。 NCC厚度保持在6至10埃范围内以减少Rp,并避免Fe(Si)颗粒不具有足够的直径以桥接上部和下部CoFeB层之间的距离。 可以在覆盖层中的Ru层下方插入FeSiO层,以防止Ru在上部CoFeB自由层中引起高阻尼常数。

    High performance MTJ element for STT-RAM and method for making the same
    70.
    发明授权
    High performance MTJ element for STT-RAM and method for making the same 有权
    用于STT-RAM的高性能MTJ元件和制作相同的方法

    公开(公告)号:US08080432B2

    公开(公告)日:2011-12-20

    申请号:US12803190

    申请日:2010-06-21

    摘要: A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20. of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

    摘要翻译: 形成利用自旋角动量转移的STT-MTJ MRAM单元的形成方法,作为改变自由层的磁矩方向的机构。 该器件包括形成在被钉扎层的Ar离子等离子体平滑表面上的IrMn钉扎层,SyAP钉扎层,自然氧化的结晶的MgO隧道势垒层,在一个实施例中,包含非晶态的自由层 Co60Fe20B20层。 分别在3和6埃的Fe的两个结晶层之间形成约20埃的厚度。 自由层的特征在于低吉尔伯特阻尼因子和对传导电子的非常强的偏振作用。 所得到的电池具有低临界电流,高dR / R,并且多个这样的电池将呈现电阻和钉扎层磁化角分散的低变化。