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公开(公告)号:US5943501A
公开(公告)日:1999-08-24
申请号:US884050
申请日:1997-06-27
CPC分类号: G06F9/5016 , G06F12/0813 , G06F9/50
摘要: A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.