公开(公告)号：US07994851B2

公开(公告)日：2011-08-09

申请号：US12511323

申请日：2009-07-29

申请人： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC分类号： H04L27/06 ,  H03D3/18

CPC分类号： H04L27/233 ,  H04L27/2338

摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.

摘要翻译： 使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。 可以降低功耗并简化电路实现。

公开(公告)号：US07973368B2

公开(公告)日：2011-07-05

申请号：US12122982

申请日：2008-05-19

申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/66462

摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

摘要翻译： 提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。 在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部 在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。 因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

公开(公告)号：US07961038B2

公开(公告)日：2011-06-14

申请号：US12631637

申请日：2009-12-04

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03B1/00

CPC分类号： G05B1/03

摘要： A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

摘要翻译： 提供了数字比例积分环路滤波器。 第一比例放大单元将相位误差值乘以第一比例环路增益，并且第一积分放大单元将相位误差累积值乘以第一积分环路增益。 第二比例放大单元将相位误差值乘以第二比例环路增益，第二积分放大单元将相位误差累积值乘以第二积分环路增益。 第一偏移值生成单元通过从第一比例环增益中减去第二比例环增益并将结果值乘以相位误差平均值来生成第一偏移值，第二偏移值生成单元通过减去第二偏移值生成单位生成第二偏移值 来自第一积分环路增益的第二积分环路增益，并将得到的值乘以相位误差累积平均值。

公开(公告)号：US07902930B2

公开(公告)日：2011-03-08

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03K3/03

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20100134334A1

公开(公告)日：2010-06-03

申请号：US12628186

申请日：2009-11-30

申请人： Jae Hoon SHIM ,  Hyun Kyu Yu

发明人： Jae Hoon SHIM ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： H03F3/005

摘要： There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator comparing an output DC offset value of a discrete-time amplifier and filter on the basis of the initial voltage value with a preset output DC offset value when the discrete-time amplifier and filter and the load capacitor are connected to each other; and a controller changing the input code value of the digital-analog converter according to comparison result of the comparator.

摘要翻译： 提供了数字直流（DC）偏移校正方法和装置。 该装置包括数模转换器，根据输入代码值对负载电容器充电并产生负载电容器的初始电压值; 当离散时间放大器和滤波器和负载电容器彼此连接时，比较器将基于初始电压值的离散时间放大器和滤波器的输出DC偏移值与预设输出DC偏移值进行比较; 以及根据比较器的比较结果改变数模转换器的输入代码值的控制器。

公开(公告)号：US07626473B2

公开(公告)日：2009-12-01

申请号：US11872026

申请日：2007-10-14

申请人： Ho Young Kim ,  Hae Cheon Kim ,  Hyun Kyu Yu ,  Young Jun Chong

发明人： Ho Young Kim ,  Hae Cheon Kim ,  Hyun Kyu Yu ,  Young Jun Chong

IPC分类号： H01P5/02 ,  H01P3/08

CPC分类号： H01P3/00

摘要： Provided is a signal transmission line for a millimeter-wave band. The signal transmission line includes: a dielectric substrate; an input line formed on the dielectric substrate; a pair of serial transmission lines formed on the dielectric substrate, the serial transmission lines being branched at, separated from, and electromagnetically connected in series with one end of the input line; a pair of parallel transmission lines respectively formed on the dielectric substrate at both sides of the input line and the serial transmission lines, and having both ends separated from and electromagnetically connected in parallel with one end of each of the input line and the serial transmission lines; and a pair of wires electrically connected between the other ends of the parallel transmission lines and a connection pad of a monolithic microwave integrated circuit (MMIC). An electrical signal of about 57 to 63 GHz generated from a monolithic microwave integrated circuit (MMIC) can be efficiently transferred.

摘要翻译： 提供了一种用于毫米波段的信号传输线。 信号传输线包括：电介质基片; 形成在电介质基板上的输入线; 形成在电介质基板上的一对串行传输线，串联传输线与输入线的一端分离并分离并与之电磁连接; 分别在输入线和串行传输线的两侧形成在电介质基板上的一对平行传输线，并且其两端与输入线和串行传输线的一端分开并与之并联电磁连接 ; 以及电连接在并行传输线的另一端之间的一对电线和单片微波集成电路（MMIC）的连接焊盘。 可以有效地传送从单片微波集成电路（MMIC）产生的约57至63GHz的电信号。

公开(公告)号：US20090261481A1

公开(公告)日：2009-10-22

申请号：US12208512

申请日：2008-09-11

申请人： Jong Tae MOON ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

发明人： Jong Tae MOON ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

IPC分类号： H01L23/52 ,  H01L21/66 ,  H01L21/00

CPC分类号： H01L23/10 ,  B81B7/007 ,  B81C2203/0118 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2224/05599

摘要： Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.

摘要翻译： 提供了一种晶片级封装，其中可以容易地在内部器件和封装外部之间形成通信线，以及制造晶片级封装的方法。 晶片级封装包括具有第一内部器件的空腔的第一衬底，形成在第一衬底上并与第一内部器件电连接的输入/输出（I / O）焊盘，设置在第一衬底上的第二衬底 第一衬底并且从其中除去对应于I / O焊盘的部分，以及焊接第一和第二衬底的焊料。 根据晶片级封装及其制造方法，上下基板被切割成不同的切割宽度，或者在上基板上形成孔，使得可以容易地形成内部装置的连通线，而不需要 穿过基底的过程。 因此，与使用通孔工艺制造的常规晶片级封装相比，可以简化制造工艺并降低生产成本。

公开(公告)号：US20080129392A1

公开(公告)日：2008-06-05

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03B27/00 ,  H03B5/12

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20070134852A1

公开(公告)日：2007-06-14

申请号：US11523212

申请日：2006-09-19

申请人： Sang Jin Byun ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Hyun Kyu Yu

IPC分类号： H01L21/82

CPC分类号： H01L27/0207

摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

摘要翻译： 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。

公开(公告)号：US06668035B2

公开(公告)日：2003-12-23

申请号：US10179840

申请日：2002-06-24

申请人： Seon Ho Han ,  Jang Hong Choi ,  Jae Hong Jang ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Jang Hong Choi ,  Jae Hong Jang ,  Hyun Kyu Yu

IPC分类号： H03K2100

CPC分类号： H03M7/3022 ,  H03L7/1978

摘要： The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

摘要翻译： 本发明涉及一种delta-sigma分数型分频器的结构。 分频器结构增加了Δ-Σ调制器的外部输入值和输出值，以调制吞咽计数器的值。 因此，本发明可以提供一种Δ-Σ分数分频器，其结构简单，并且可以获得具有宽带频率混合能力的Δ-Σ模式的结构的效果。