公开(公告)号：US07495587B2

公开(公告)日：2009-02-24

申请号：US11730795

申请日：2007-04-04

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： H03M5/00

CPC分类号： G11C7/1006 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/406

摘要： A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.

摘要翻译： 用于减少刷新存储器所需的功率消耗的方法和装置可以接收已经使用数据总线反转（DBI）编码的数据，DBI数据具有在零和DBI最大值之间的不同情况下的零个数之间的第一增量，余额 对DBI数据进行编码以平衡DBI数据上的零数量，并且输出具有大于零且小于或等于DBI最大值的最小数量和等于最小值的最大数量的不同情况下的零个数的数据 数字加上第二个delta，第二个delta小于第一个delta。

公开(公告)号：US20110242916A1

公开(公告)日：2011-10-06

申请号：US13048219

申请日：2011-03-15

申请人： Ho-Seok Seol ,  Young-Soo Sohn ,  Dong-Min Kim ,  Jin-Il Lee ,  Kwang-II Park ,  Seung-Jun Bae ,  Sang-Hyup Kwak

发明人： Ho-Seok Seol ,  Young-Soo Sohn ,  Dong-Min Kim ,  Jin-Il Lee ,  Kwang-II Park ,  Seung-Jun Bae ,  Sang-Hyup Kwak

IPC分类号： G11C7/00 ,  H03K19/003

CPC分类号： H03K19/018585 ,  G06F2213/0038 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/1057 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292

摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.

摘要翻译： 片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。 终端电阻单元为连接到外部引脚的传输线提供终端阻抗。 终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

公开(公告)号：US20110158011A1

公开(公告)日：2011-06-30

申请号：US12948193

申请日：2010-11-17

申请人： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-Il Park

发明人： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-Il Park

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C7/10 ,  G11C7/02

摘要： A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

摘要翻译： 提供了一种存储器接口电路，包括：第一信号输出电路，被配置为经由第一信号线将第一信号输出到第一I / O端子; 第二信号输出电路，被配置为经由第二信号线将第二信号输出到第二I / O端子; 以及噪声消除电路，其具有至少一个相位调整元件和至少一个增益调整元件，以减少由于在第一信号线上存在第一信号而在第二信号线上感应到的噪声信号，其中第二信号线是 设置在第一信号线附近。

公开(公告)号：US20100103952A1

公开(公告)日：2010-04-29

申请号：US12655624

申请日：2010-01-04

申请人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

发明人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

IPC分类号： H04L29/02

CPC分类号： H03M5/145

摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

摘要翻译： 数据通信设备或系统包括前同步码单元和数据接口。 前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。 第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。 所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。 每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

公开(公告)号：US20090097339A1

公开(公告)日：2009-04-16

申请号：US12236978

申请日：2008-09-24

申请人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

发明人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18

摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.

摘要翻译： 集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。 内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。 例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。 或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。 这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

公开(公告)号：US20060176988A1

公开(公告)日：2006-08-10

申请号：US11345451

申请日：2006-02-02

申请人： Young-Soo Sohn ,  Seung-Jun Bae ,  Hong-Jun Park ,  Jung-Hwan Choi

发明人： Young-Soo Sohn ,  Seung-Jun Bae ,  Hong-Jun Park ,  Jung-Hwan Choi

IPC分类号： H04B1/10

CPC分类号： H04L25/03038 ,  H04L7/0058

摘要： A receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient based on the plurality of internal clock signals and the input signal. The equalization receiving unit may adjust a received data signal based on the determined offset value and equalization coefficient.

摘要翻译： 一种接收装置及其方法。 在一个示例中，接收装置可以包括基于接收的外部时钟信号产生多个内部时钟信号的时钟产生单元和接收多个内部时钟信号的均衡接收单元和输入信号。 均衡接收单元可以基于多个内部时钟信号和输入信号确定偏移值和均衡系数。 均衡接收单元可以基于确定的偏移值和均衡系数来调整接收的数据信号。

公开(公告)号：US08395955B2

公开(公告)日：2013-03-12

申请号：US12948193

申请日：2010-11-17

申请人： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-Il Park

发明人： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-Il Park

IPC分类号： G11C7/02

CPC分类号： G11C7/10 ,  G11C7/02

摘要： A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

摘要翻译： 提供了一种存储器接口电路，包括：第一信号输出电路，被配置为经由第一信号线将第一信号输出到第一I / O端子; 第二信号输出电路，被配置为经由第二信号线将第二信号输出到第二I / O端子; 以及噪声消除电路，其具有至少一个相位调整元件和至少一个增益调整元件，以减少由于在第一信号线上存在第一信号而在第二信号线上感应到的噪声信号，其中第二信号线是 设置在第一信号线附近。

公开(公告)号：US20110298499A1

公开(公告)日：2011-12-08

申请号：US13110242

申请日：2011-05-18

申请人： Ho-Seok Seol ,  Seung-Jun Bae

发明人： Ho-Seok Seol ,  Seung-Jun Bae

IPC分类号： G05F3/16

CPC分类号： G11C5/147 ,  G11C11/4074

摘要： An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage.

摘要翻译： 内部电压发生器包括比较单元，驱动电路和偏置单元。 比较单元比较参考电压和内部电压，并且被配置为输出基于参考电压和内部电压之间的差的比较电压。 驱动电路接收比较电压和外部电源电压，并且被配置为响应于比较电压将内部电压输出到输出节点。 偏置单元接收内部电压，并且被配置为考虑到内部电压的电平，自适应地调节流过偏置单元的偏置电流以驱动比较单元。

公开(公告)号：US07737748B2

公开(公告)日：2010-06-15

申请号：US11986841

申请日：2007-11-27

申请人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

发明人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

IPC分类号： H03K3/017

CPC分类号： H03K3/35613 ,  H03K3/017

摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.

摘要翻译： 提供半导体器件的电平移位器和控制占空比的方法。 电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管 施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出 控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

公开(公告)号：US20080186075A1

公开(公告)日：2008-08-07

申请号：US11986841

申请日：2007-11-27

申请人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

发明人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/017

摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.

摘要翻译： 提供半导体器件的电平移位器和控制占空比的方法。 电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管 施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出 控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。