公开(公告)号：US20120062102A1

公开(公告)日：2012-03-15

申请号：US12807688

申请日：2010-09-10

申请人： David Chiang

发明人： David Chiang

IPC分类号： H01J1/62 ,  H01K1/30 ,  H01J9/24 ,  H01J5/50

CPC分类号： H01J29/20 ,  F21K9/232 ,  F21K9/27 ,  F21K9/64 ,  F21K9/90 ,  F21V3/12 ,  F21V29/70 ,  F21V29/89 ,  F21Y2115/10 ,  G09F13/20 ,  G09F13/22 ,  G09F13/26 ,  G09F13/28

摘要： A light apparatus includes s light arrangement and a highlighting element. The light arrangement includes a light housing, at least a connector coupling with the light housing for electrically connecting to a power supply source, and at least a light source received in the light housing for generating a non-neon light to penetrate through the light housing. The highlighting element is provided at the light housing and arranged in such a manner that when the light passes through the light housing, the highlighting element creates a neon light emitting effect at the light arrangement.

摘要翻译： 光装置包括灯的布置和高亮元件。 光装置包括一个灯壳体，至少一个与灯壳体连接的用于电连接到电源的连接器，以及至少一个容纳在灯壳中的光源，用于产生非氖光以穿过灯壳体 。 突出元件设置在灯壳体处并且以这样的方式布置，使得当光线通过灯壳体时，高亮元件在光布置处产生霓虹灯发光效果。

公开(公告)号：US20100071239A1

公开(公告)日：2010-03-25

申请号：US12284659

申请日：2008-09-23

申请人： David Chiang ,  John Chiang

发明人： David Chiang ,  John Chiang

IPC分类号： G09F13/06

CPC分类号： G09F13/04 ,  G09F13/0413 ,  G09F13/22 ,  G09F2013/1895 ,  G09F2013/222

摘要： An illuminating sign includes a base panel; an illuminating unit, and a front casing. The front casing includes a metallic light blocking frame attached on the base panel for enhancing a strength of the front casing, wherein the light blocking frame has a plurality of through slots spacedly formed thereon, a plurality of illuminating members securely supported in front of the base panel, and a highlighting element provided at the illuminating members, wherein when the illumination unit is operated for generating the light towards the front casing, the metallic light blocking frame not only blocks the light passing therethrough but also facilitates efficient and effective heat transfer from the illuminating unit to an exterior of the front casing for preventing the illuminating unit from being overheat within the front casing.

摘要翻译： 照明标志包括基板; 照明单元和前壳体。 前壳体包括安装在基板上的金属遮光框，用于增强前壳体的强度，其中遮光框架具有间隔地形成在其上的多个通孔，多个照明构件牢固地支撑在底座的前面 面板和设置在照明构件上的高亮元件，其中当照明单元被操作以朝向前壳体产生光时，金属遮光框架不仅阻挡穿过其中的光，而且还有助于从 照明单元到前壳体的外部，用于防止照明单元在前壳体内过热。

公开(公告)号：US20090052395A1

公开(公告)日：2009-02-26

申请号：US11892330

申请日：2007-08-22

申请人： Derek Hongwei Bao ,  David Chiang

发明人： Derek Hongwei Bao ,  David Chiang

IPC分类号： H04Q7/00

CPC分类号： H04W48/12 ,  H04W48/16 ,  H04W84/045

摘要： Femto cells that extend mobile network coverage into customer premises operate in a frequency band typically assigned to a macro network. As disclosed, to facilitate system discovery and registrations of mobile stations with femto cells, a carrier designates one the channels within the band as a primary channel for its femto cells. For example, neighbor list messages transmitted by macro network base stations can provide frequency and PN code information directing mobile stations to search the primary channel for a PN code of the femto cells. Also, a mobile station PRL may identify femto cells by SID/NID. The SID is that of the carrier's macro network, whereas the NID may be a NID of the macro network or one specifically assigned to femto cell operations. The PRL uses frequency acquisition information for the femto cells that is the same as or similar to that for one of the macro networks.

摘要翻译： 将移动网络覆盖扩展到客户驻地的毫微微小区在通常分配给宏网络的频带中操作。 如所公开的，为了促进具有毫微微小区的移动站的系统发现和注册，载波将频带内的信道指定为其毫微微小区的主要信道。 例如，由宏网络基站发送的邻居列表消息可以提供频率和PN码信息，其指示移动台在主信道上搜索毫微微小区的PN码。 此外，移动站PRL可以通过SID / NID来识别毫微微小区。 SID是运营商的宏网络的SID，而NID可以是宏网络的NID或专门分配给毫微微小区操作的NID。 PRL使用与一个宏网络相同或类似的毫微微小区的频率获取信息。

公开(公告)号：US5898602A

公开(公告)日：1999-04-27

申请号：US591841

申请日：1996-01-25

申请人： Daniel J. Rothman ,  David Chiang

发明人： Daniel J. Rothman ,  David Chiang

IPC分类号： G06F7/575 ,  H03K19/177 ,  G06F7/38 ,  G06F7/50

CPC分类号： G06F7/575 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： An improved arithmetic logic unit (ALU) of an erasable-programmable logic device (EPLD) with a flexible, programmable carry function allows a broad range of functions to be implemented. The inventive circuit utilizes a separately configurable carry chain with multiple logic and arithmetic function capabilities.

摘要翻译： 具有灵活的可编程进位功能的可擦除可编程逻辑器件（EPLD）的改进的算术逻辑单元（ALU）允许实现广泛的功能。 本发明的电路使用具有多个逻辑和算术功能能力的单独配置的进位链。

公开(公告)号：US5742178A

公开(公告)日：1998-04-21

申请号：US740118

申请日：1996-10-22

申请人： Jesse H. Jenkins, IV ,  Nicholas Kucharewski, Jr. ,  David Chiang

发明人： Jesse H. Jenkins, IV ,  Nicholas Kucharewski, Jr. ,  David Chiang

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/00361 ,  H03K19/018585 ,  H03K19/1736 ,  H03K19/1778

摘要： In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.

摘要翻译： 在具有多个外部引脚的可编程逻辑器件中，每个可由可编程逻辑块控制的输出驱动结构驱动，插入诸如或门或可编程上拉或下拉开关的逻辑器件 在输出驱动结构的输入端和可编程逻辑块或控制输出驱动器的其他内部逻辑块之间。 该插入结构允许宏单元用于内部逻辑，而输出驱动结构用于稳定电源或接地电压。

公开(公告)号：US5483478A

公开(公告)日：1996-01-09

申请号：US225192

申请日：1994-04-08

申请人： David Chiang

发明人： David Chiang

IPC分类号： G06F7/50 ,  G06F7/508

CPC分类号： G06F7/508 ,  G06F7/507

摘要： A carry-lookahead structure for programmable architectures includes a number of M-bit carry lookahead units, each M-bit unit having two parallel programmable carry paths having AND gates controlled by configuration bits to program the beginning and end of an operating carry chain within the M-bit units, as well as the beginning locations in each unit, one path generating a first set of carry bits for the case of the carry-in equal to 0, and the other generating a second set of carry bits for the case of the carry-in equal to 1, and at least one multiplexer controlled by the carry-in for selecting one of the two carries at the most significant bit of the first and second sets of carry bits as carry-out of the unit. Each M-bit unit may further include multiplexers controlled by the carry-in for selecting which of the first and second sets of carry bits are the correct carry bits for addition and M sum logic elements for generating the outputs of sum bits. An alternative is an adder in which the precomputation of the sums is performed for the two possible values of carry-in in each M-bit unit, providing two sets of sum bits, and where multiplexers select which of the two sets of the sum bits is the correct sum and which of the two carry bits produced in the most significant bit of the unit is used as the carry-out of the unit in response to the actual carry-in value of the unit.

摘要翻译： 用于可编程架构的进位 - 前瞻结构包括多个M位进位先行单元，每个M位单元具有两个并行可编程进位路径，其具有由配置位控制的与门，以对操作进位链的开始和结束进行编程， M位单元以及每个单元中的开始位置，一个路径在进位的情况下产生等于0的第一组进位位，另一个路径生成第二组进位位，用于 该进位等于1，以及至少一个由进位输入控制的多路复用器，用于选择第二和第二进位位集合中最高有效位之间的两个载波之一，作为该单元的进位。 每个M位单元还可以包括由进位控制的多路复用器，用于选择第一和第二组进位位中的哪一个是用于加法的正确进位位和用于产生和位的输出的M和逻辑元件。 替代方案是一个加法器，其中对每个M位单元中的两个可能的进位值执行和的预计算，提供两组和位，并且其中多路复用器选择两个和位中的哪一个 是单位的最高有效位中产生的两个进位中的哪一个作为单元的进位值，作为单元的实际进位值被响应。

公开(公告)号：US5302866A

公开(公告)日：1994-04-12

申请号：US32919

申请日：1993-03-18

申请人： David Chiang ,  Thomas Y. Ho ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg

发明人： David Chiang ,  Thomas Y. Ho ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K3/289

CPC分类号： H03K19/1737 ,  H03K19/17716

摘要： An input block for PLDs programmable logic devices) has a flip-flop including a master latch and a slave latch, a pad for inputting data, configuration bits, and a global clock input signal for clocking the input data to the flip-flop means. The flip-flop is controlled by the configuration bits so as to function alternatively as a register, a latch or transparently. The input block further includes at least one clock enable signal input terminal and logic elements responding to the configuration bits for providing the clock enable signal for the register function as well as the latch function of the flip-flop.

摘要翻译： 用于PLD可编程逻辑器件的输入块）具有包括主锁存器和从锁存器的触发器，用于输入数据的配置位，配置位和用于将输入数据计时到触发器装置的全局时钟输入信号。 触发器由配置位控制，以便作为寄存器，锁存器或透明地替代地起作用。 输入块还包括响应于配置位的至少一个时钟使能信号输入端和逻辑元件，用于为寄存器功能提供时钟使能信号以及触发器的锁存功能。

公开(公告)号：US5268598A

公开(公告)日：1993-12-07

申请号：US043146

申请日：1993-03-31

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03R19/177

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。

公开(公告)号：US5097208A

公开(公告)日：1992-03-17

申请号：US622615

申请日：1990-12-05

申请人： David Chiang

发明人： David Chiang

IPC分类号： G01R29/027

CPC分类号： G01R29/0273

摘要： Apparatus and a method for measuring average individual gate delays on integrated circuit wafers without the need for high bandwidth is provided. A chain of gates is provided on the wafer. A reference signal is propagated through the chain to produce a delayed signal. The delayed signal is logically combined with the reference signal to provide a periodic train of pulses whose period is proportional to that of the reference signal. The pulse widths represent the total gate delay of the chain, and are determined by statistically sampling the pulse train to determine its duty cycle. The apparatus and method are compatible with automated testing equipment and methods which can be synchronized with the reference signal.

摘要翻译： 提供了一种用于测量集成电路晶片上的平均单个门延迟而不需要高带宽的装置和方法。 在晶片上设置一个栅极链。 参考信号通过链传播以产生延迟信号。 延迟信号与参考信号逻辑组合以提供其周期与参考信号的周期成比例的周期性脉冲串。 脉冲宽度表示链的总门延迟，并且通过统计采样脉冲串来确定其占空比来确定。 该装置和方法与可与参考信号同步的自动化测试设备和方法兼容。

公开(公告)号：US5091661A

公开(公告)日：1992-02-25

申请号：US587075

申请日：1990-09-24

申请人： David Chiang

发明人： David Chiang

IPC分类号： G11C17/00 ,  G11C16/04 ,  H03K19/003 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/00346

摘要： Methods and apparatus are provided for reducing the possibility of erroneous operation in integrated circuit structures such as Programmable Interconnector arrays (PIAs) in high-density Programmable Logic Devices (PLDs) due to unintentional transmission of coherent switching transients from word lines to bit lines. The logical states of appropriate PIA word lines are inverted in a way that reduces the possibility of coherent switching of multiple word lines in the word lines and bit line swithcing matrix. This technique requires little or no area overhead and is completely transparent to the user. It changes the perforamnce of the PLDs so that situations in which worst-case conditions apply become highly unlikely, whereas these same worst-case conditions are very likely to arise in prior PLDs.