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    Semiconductor device and manufacture thereof
    63.
    发明授权
    Semiconductor device and manufacture thereof 有权

    公开(公告)号：US11069575B2

    公开(公告)日：2021-07-20

    申请号：US16109435

    申请日：2018-08-22

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Jiquan Liu

    IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L21/8238

    摘要： A semiconductor device and its manufacturing method are presented, relating to semiconductor technology. The manufacturing method comprises: providing a substrate structure comprising a substrate, a source region on the substrate, and a gate structure on the source region; forming cavities on two opposing sides of the gate structure; epitaxially growing electrodes in the cavities, with each electrode comprising an electrode body and an amorphous layer on the electrode body; forming an dielectric layer on the substrate structure covering the electrodes and the gate structure; etching the dielectric layer to form a contact hole exposing the amorphous layer; forming a conductive adhesive layer on the bottom and on the side of the contact hole; and forming a contact component on the conductive adhesive layer filling the contact hole. In this semiconductor device, the adhesive layer may be directly formed on the amorphous layer, resulting in improved performance of the device.

    Semiconductor device and forming method thereof
    64.
    发明授权
    Semiconductor device and forming method thereof 有权

    公开(公告)号：US11069572B2

    公开(公告)日：2021-07-20

    申请号：US16806062

    申请日：2020-03-02

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Ze Jun He ,  Jun Ling Pang

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311

    摘要： Semiconductor device and formation method are provided. The method includes providing a substrate, a first fin and a second fin on the substrate, an isolation structure covering a portion of sidewalls of the first and second fins, a gate structure across the first fin or the second fin, a first doped source/drain region in the first fin, a second doped source/drain region in the second fin, and an interlayer dielectric layer on the isolation structure, the first and second fins, and the gate structure. A first through hole is formed in the interlayer dielectric layer, exposing the first doped source/drain region or the second doped source/drain region. A second through hole is formed in the interlayer dielectric layer on the isolation structure to connect to the first through hole. A first plug is formed in the first through hole and a second plug is formed in the second through hole.

    Regulator circuit and manufacture thereof
    65.
    发明授权
    Regulator circuit and manufacture thereof 有权

    公开(公告)号：US11068009B2

    公开(公告)日：2021-07-20

    申请号：US16044949

    申请日：2018-07-25

    申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

    发明人： Jun Wang

    IPC分类号： G05F3/26 ,  G05F3/24 ,  H03F1/02

    摘要： A regulator circuit and its manufacturing method are presented, relating to semiconductor technology. The regulator circuit comprises a mirror current source comprising two current output nodes; a depletion MOS transistor comprising a drain connected to one current output node of the mirror current source, a gate connected to the ground, and a source; an enhancement MOS transistor comprising a drain connected to the other current output node of the mirror current source, and a source connected to the ground; a first resistance device comprising a first node connected to the drain of the depletion MOS transistor, and a second node connected to a gate of the enhancement MOS transistor; and a second resistance device comprising a first node connected to the first resistance device, and a second node connected to the ground. This regulator circuit consumes less power than its conventional counterparts.

    CORRECTION METHOD OF MASK LAYOUT AND MASK CONTAINING CORRECTED LAYOUT
    66.
    发明申请
    CORRECTION METHOD OF MASK LAYOUT AND MASK CONTAINING CORRECTED LAYOUT 有权

    公开(公告)号：US20210216008A1

    公开(公告)日：2021-07-15

    申请号：US17037613

    申请日：2020-09-29

    申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： Yaojun DU

    IPC分类号： G03F1/70 ,  G06F30/392 ,  G03F1/44

    摘要： Correction method of mask layout and mask containing corrected layout are provided. The method includes providing a target layout including a plurality of main patterns. Each main pattern includes a first side and an opposite second side. Extending directions of the first side and the second side are perpendicular to a first direction. Each main pattern also includes a third side and an opposite fourth side. Extension directions of the third side and the fourth side are perpendicular to a second direction. The second direction and the first direction are perpendicular to each other. The method also includes acquiring position information of each main pattern, and obtaining position information of auxiliary patterns adjacent to each main pattern. The method also includes, according to the position information of the auxiliary patterns adjacent to each main pattern, arranging the auxiliary patterns adjacent to each main pattern around each main pattern.

    Semiconductor structure and method for forming the same
    67.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US11063119B2

    公开(公告)日：2021-07-13

    申请号：US16601855

    申请日：2019-10-15

    申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： Nan Wang

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

    摘要： Disclosed are a semiconductor structure and a method for forming same. A forming method includes: forming a first inside wall in a first groove; etching an initial channel laminated layer and an initial fin after the first inside wall is formed, where the residual initial fin is used as a fin, and the residual initial channel laminated layer located on the fin is used to form a channel laminated layer, the channel laminated layer includes a composite layer and a channel layer located on the composite layer, and the composite layer includes a first inside wall and a sacrificial layer located on a sidewall of the first inside wall; forming a pseudo gate structure across the channel laminated layer after the fin is formed; forming a source-drain doping layer in channel laminated layers on two sides of the pseudo gate structure; and removing the pseudo gate structure and the sacrificial layer after the source-drain doping layer is formed, and forming a metal gate structure at positions of the pseudo gate structure and the sacrificial layer. The first inside wall provides support for the channel layer. Therefore, even though the channel layer is relatively long, the channel layer cannot easily deform or collapse under the gravity effect, thereby optimizing the electrical performance of the semiconductor structure.

    Semiconductor device and fabrication method thereof
    69.
    发明授权
    Semiconductor device and fabrication method thereof 有权

    公开(公告)号：US11062962B2

    公开(公告)日：2021-07-13

    申请号：US16502295

    申请日：2019-07-03

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Fei Zhou

    IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

    摘要： Semiconductor devices and fabrication methods are provided. An exemplary semiconductor device includes a semiconductor substrate having a first region. The first region includes a first middle region and a first edge region adjacent to and surrounding the first middle region; and a surface of the first middle region of the semiconductor substrate is higher than a surface of the first edge region of the semiconductor substrate. The semiconductor device also includes a plurality of first fins discretely formed on the first middle region of the semiconductor substrate; and an isolation structure formed on the first middle region of the semiconductor substrate and the first edge region of the semiconductor substrate and covering portions of sidewall surfaces of the first fins.

    SEMICONDUCTOR DEVICES
    70.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210202720A1

    公开(公告)日：2021-07-01

    申请号：US17197423

    申请日：2021-03-10

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Fei ZHOU

    IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/308

    摘要： A semiconductor device includes: a substrate; a fin structure and a gate structure formed on the substrate; and a source/drain trench formed in the fin structure on each side of the gate structure. The source/drain trench includes a bottom region and a top region located above the bottom region. Along an extension direction of the fin structure, a dimension of the top region is larger than a dimension of the bottom region. Along the extension direction of the fin structure, a shortest distance from a sidewall surface of the top region of the source/drain trench to a sidewall surface of the gate structure is smaller than a shortest distance from a sidewall surface of the bottom region of the source/drain trench to the sidewall surface of the gate structure. The semiconductor device further includes a source/drain doped layer formed in the source/drain trench.