公开(公告)号：US5483203A

公开(公告)日：1996-01-09

申请号：US332973

申请日：1994-11-01

申请人： Alan P. Rottinghaus

发明人： Alan P. Rottinghaus

IPC分类号： H03C3/09 ,  H03L7/189

CPC分类号： H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/189

摘要： A frequency synthesizer 10 having a digital to analog converter (DAC) 40 and a feedback system which detects the deviation of a frequency modulated signal and aligns the detected deviation. DAC 40 provides a presteering stimulus for alignment purposes. After presteering alignment, the gain of DAC 40 is accurately set for frequency deviation because modulation is sourced from the same digital to analog converter that performs presteering.

摘要翻译： 具有数模转换器（DAC）40的频率合成器10和检测频率调制信号的偏差并对准所检测的偏差的反馈系统。 DAC 40提供了用于对准目的的预引导刺激。 在预引导对准之后，DAC 40的增益被精确地设置为频率偏差，因为调制源自执行预转向的相同的数模转换器。

公开(公告)号：US4567603A

公开(公告)日：1986-01-28

申请号：US502778

申请日：1983-06-09

申请人： William J. Howell ,  John D. Hatchett

发明人： William J. Howell ,  John D. Hatchett

IPC分类号： H03C3/09 ,  H04L27/12 ,  H03C3/06

CPC分类号： H03C3/0933 ,  H03C3/0925 ,  H04L27/12

摘要： A frequency generator in which the PLL frequency synthesizer and the VCO are directly modulated by an input serial data stream for providing an FSK modulated RF output signal useful in narrowband data communication systems. The serial data stream may alternatively modulate either the PLL frequency synthesizer or the VCO alone.

摘要翻译： 一种频率发生器，其中PLL频率合成器和VCO由用于提供在窄带数据通信系统中有用的FSK调制的RF输出信号的输入串行数据流直接调制。 串行数据流也可以单独调制PLL频率合成器或VCO。

公开(公告)号：US4562414A

公开(公告)日：1985-12-31

申请号：US565947

申请日：1983-12-27

申请人： Donald L. Linder ,  William R. Murphy

发明人： Donald L. Linder ,  William R. Murphy

IPC分类号： H03C3/09 ,  H03C3/00

CPC分类号： H03C3/0983 ,  H03C3/0933 ,  H03C3/0941

摘要： There is disclosed a new and improved frequency modulation system and method for providing a frequency modulated signal which varies in frequency from a center frequency in response to the amplitude of an analog modulating signal. The system and method utilizes a frequency shift synthesizer to provide the frequency modulated signal and digital techniques for quantizing the amplitude modulating signal and providing dividing factors to the frequency shift synthesizer responsive to the amplitude quantization.

摘要翻译： 公开了一种新的改进的频率调制系统和方法，用于响应于模拟调制信号的振幅，提供频率随中心频率变化的频率调制信号。 该系统和方法利用频移合成器提供频率调制信号和用于量化幅度调制信号的数字技术，并且响应于幅度量化向频移合成器提供分频因子。

公开(公告)号：US4477919A

公开(公告)日：1984-10-16

申请号：US251572

申请日：1981-04-06

申请人： Jaime A. Borras ,  Ruben J. Gonzalez

发明人： Jaime A. Borras ,  Ruben J. Gonzalez

IPC分类号： H03C3/09 ,  H03C3/22 ,  H03D13/00 ,  H03J5/02 ,  H03K23/66 ,  H03L7/08 ,  H03L7/193 ,  H03L7/199 ,  H04B1/40 ,  H03K21/36

CPC分类号： H03K21/38 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/227 ,  H03D13/005 ,  H03J5/0281 ,  H03K23/667 ,  H03L7/0802 ,  H03L7/193 ,  H03L7/199 ,  H04B1/405

摘要： A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. A programmable divider coupled to a reference oscillator source is compared with the output of the synchronous counter in a digital and analog phase detector. The phase detector supplies signals through a loop filter to apply the appropriate voltage to the voltage controlled oscillator. The phase detector includes means to rapid advance the voltage controlled oscillator to cause frequency tuning.

摘要翻译： 公开了能够调谐到多个通信信道的频率合成收发器。 收发器包括接收器部分和发射器部分，其耦合到合成器，其产生适当的注入信号以实现调谐。 频率合成器包括一个多位开关，该多位开关访问可编程只读存储器中的各种可寻址存储器位置，其中存储适当的除数以使合成器调谐到合适的通信信道。 区域选择开关使分组和通道容易检索。 除数被提供给单个同步二进制吞咽计数器，其与双模预分频器一起工作以监视压控振荡器的频率输出。 耦合到参考振荡器源的可编程分频器与数字和模拟相位检测器中的同步计数器的输出进行比较。 相位检测器通过环路滤波器提供信号，以将适当的电压施加到压控振荡器。 相位检测器包括用于快速推进压控振荡器以引起频率调谐的装置。

公开(公告)号：US4472820A

公开(公告)日：1984-09-18

申请号：US251658

申请日：1981-04-06

申请人： Jaime A. Borras

发明人： Jaime A. Borras

IPC分类号： H03C3/09 ,  H03C3/22 ,  H03D13/00 ,  H03J5/02 ,  H03K23/66 ,  H03L7/08 ,  H03L7/193 ,  H03L7/199 ,  H04B1/40 ,  H03K21/36

CPC分类号： H03K21/38 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/227 ,  H03D13/005 ,  H03J5/0281 ,  H03K23/54 ,  H03K23/667 ,  H03L7/0802 ,  H03L7/193 ,  H03L7/199 ,  H04B1/405

摘要： In a transceiver, a synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory (PROM), where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. In the swallow counting device, two latches receive divisor related information supplied by the PROM. When the sampled state of a single up counter reaches a first latched number, the prescaler changes the modulus. Synchronous counting then continues, without reprogramming new values. When the up counter reaches a second latched number, a predetermined frequency ratio has been achieved, and the counter is reset.

摘要翻译： 在收发器中，合成器包括一个多位开关，该多位开关访问可编程只读存储器（PROM）中的各种可寻址存储器位置，其中存储适当的除数以使合成器调谐到合适的通信信道。 区域选择开关使分组和通道容易检索。 除数被提供给单个同步二进制吞咽计数器，其与双模预分频器一起工作以监视压控振荡器的频率输出。 在吞咽计数装置中，两个锁存器接收由PROM提供的除数相关信息。 当单个向上计数器的采样状态达到第一个锁存数时，预分频器将改变模数。 然后，同步计数继续，而不重新编程新值。 当向上计数器达到第二个锁存数时，已经达到预定的频率比，并且计数器被复位。

公开(公告)号：US09948449B2

公开(公告)日：2018-04-17

申请号：US15493229

申请日：2017-04-21

申请人： SUNRISE MICRO DEVICES, INC.

发明人： Mario Lafuente ,  Paul Edward Gorday

IPC分类号： H04L7/033 ,  H04L27/12

CPC分类号： H04L7/033 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H04L7/0331 ,  H04L27/0014 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127 ,  H04L27/152 ,  H04L27/3411 ,  H04L43/50 ,  H04L2027/0055

摘要： Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

公开(公告)号：US09941889B1

公开(公告)日：2018-04-10

申请号：US15590730

申请日：2017-05-09

申请人： Beken Corporation

发明人： Dawei Guo ,  Caogang Yu

IPC分类号： H03K5/133 ,  H03L7/08 ,  H03C3/09 ,  H03L7/197 ,  H03D3/24 ,  H03K21/00 ,  G11B7/09 ,  G06F7/499

CPC分类号： H03L7/0805 ,  G06F7/49942 ,  H03C3/0933 ,  H03K5/133 ,  H03K21/00 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1976

摘要： A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.

公开(公告)号：US09634877B2

公开(公告)日：2017-04-25

申请号：US15007969

申请日：2016-01-27

申请人： SUNRISE MICRO DEVICES, INC.

发明人： Mario Lafuente ,  Paul Edward Gorday

IPC分类号： H04L27/34 ,  H04L7/033 ,  H04L12/26

CPC分类号： H04L7/033 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H04L7/0331 ,  H04L27/0014 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127 ,  H04L27/152 ,  H04L27/3411 ,  H04L43/50 ,  H04L2027/0055

摘要： Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

公开(公告)号：US20160020773A1

公开(公告)日：2016-01-21

申请号：US14332614

申请日：2014-07-16

申请人： VIA Telecom Co., Ltd.

发明人： Shih-An YU ,  Sen-You LIU ,  Fang-Ren LIAO ,  Yi-Pei SU

IPC分类号： H03L7/08 ,  H02M3/07 ,  H03B5/32 ,  H03L7/099 ,  H03L7/093

CPC分类号： H03B5/32 ,  H02M3/07 ,  H03C3/0933 ,  H03L7/087 ,  H03L7/0893 ,  H03L7/18 ,  H03L7/1972 ,  H03L7/1976

摘要： A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

摘要翻译： 锁相环电路包括相位检测器，电荷泵，电容器和电容器倍增器。 相位检测器接收参考频率和反馈频率以产生上/下信号。 包括正节点和负节点的电荷泵接收上/下信号以产生第一电流。 电容器耦合到负节点。 耦合到负节点的电容器倍增器产生第二电流，其是第一电流除以第一缩放数。

公开(公告)号：US20150229317A1

公开(公告)日：2015-08-13

申请号：US14616192

申请日：2015-02-06

申请人： DUST NETWORKS, INC.

发明人： Thor Nelson JUNEAU ,  Mark Alan LEMKIN

IPC分类号： H03L7/18

CPC分类号： H03L7/18 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966 ,  H03C3/0975 ,  H03K3/0315 ,  H03L7/0814

摘要： A frequency synthesizer directly generates phase modulated radio-frequency (RF) signals. The frequency synthesizer includes a voltage controlled oscillator (VCO) producing a synthesized frequency signal having a frequency controlled based on a signal received at an input of the VCO. A digitally adjustable frequency divider produces a reduced frequency signal from the synthesized frequency signal. A phase digital-to-analog converter (DAC) produces a delayed version of a timing signal (e.g., the reduced frequency signal, or a reference clock signal) that is delayed according to a digital control signal. A phase detector (PD) produces a phase control signal from the reduced frequency signal and/or the delayed timing signal. A digital signal converter controls the digitally adjustable frequency divider and the phase DAC so as to cause a phase or frequency of the synthesized frequency signal output by the VCO to track a desired phase or frequency trajectory encoded in a digital signal.

摘要翻译： 频率合成器直接产生相位调制的射频（RF）信号。 频率合成器包括压控振荡器（VCO），其产生具有基于在VCO的输入处接收的信号的频率控制的合成频率信号。 数字可调分频器产生来自合成频率信号的降频信号。 相位数/模转换器（DAC）产生根据数字控制信号延迟的定时信号（例如，降频信号或参考时钟信号）的延迟版本。 相位检测器（PD）从降频信号和/或延迟的定时信号产生相位控制信号。 数字信号转换器控制数字可调分频器和相位DAC，以使由VCO输出的合成频率信号的相位或频率跟踪以数字信号编码的所需相位或频率轨迹。