公开(公告)号：US20040054957A1

公开(公告)日：2004-03-18

申请号：US10624774

申请日：2003-07-22

发明人： Christian Luetkemeyer

IPC分类号： H03M013/03

CPC分类号： H04L25/14 ,  H03M13/39 ,  H03M13/4107 ,  H03M13/4184 ,  H03M13/4192 ,  H03M13/6502 ,  H03M13/6508 ,  H03M13/6563 ,  H04L1/0054

摘要： A decoder having a memory structure which receives and stores potential symbols, with each of the potential symbols having a unique pointer associated therewith. One of the potential symbols is a most likely symbol. The most likely symbol is selected using a pointer selector which processes the unique pointers according to a predetermined selection operation and selects the most likely pointer which, in turn, is uniquely associated with the most likely symbol. The most likely pointer then is used to produce the most likely symbol. The pointer selector is a shuffle exchange network and the predetermined selection operation is a shuffle-exchange operation. The decoder can be used in systems that conform to IEEE Standard 802.3ab, e.g., gigabit Ethernet systems. The potential symbols are four-dimensional, 12-bit symbols having eight symbol states. The memory structure and pointer selector can be constituent of a maximum likelihood decoder, for example a trellis decoder, more specifically a Viterbi decoder. One such pointer selector is a shuffle exchange network which selects the most likely pointer using a shuffle exchange operation upon the unique pointers and not the potential symbols, as with previous architectures and methods.

摘要翻译： 具有存储器结构的解码器，其接收并存储潜在符号，其中每个潜在符号具有与之相关联的唯一指针。 其中一个潜在的符号是最有可能的符号。 使用指针选择器选择最可能的符号，该指针选择器根据预定的选择操作来处理唯一指针，并且选择最可能的指针，其又与最可能的符号唯一相关联。 然后，最可能的指针用于产生最可能的符号。 指针选择器是洗牌交换网络，预定的选择操作是洗牌交换操作。 解码器可用于符合IEEE标准802.3ab的系统，例如千兆以太网系统。 潜在符号是具有八个符号状态的四维的12位符号。 存储器结构和指针选择器可以是最大似然解码器的组成部分，例如网格解码器，更具体地说是维特比解码器。 一个这样的指针选择器是随机洗牌交换网络，其与先前的架构和方法一样，使用对唯一指针而不是潜在符号的随机交换操作来选择最可能的指针。

公开(公告)号：US06662331B1

公开(公告)日：2003-12-09

申请号：US09699252

申请日：2000-10-27

申请人： Inyup Kang

发明人： Inyup Kang

IPC分类号： H03M1300

CPC分类号： H03M13/3905 ,  H03M13/2975 ,  H03M13/2984 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6563

摘要： An efficient turbo decoder. The disclosed turbo decoder includes a first mode of operation in which the turbo decoder uses a first functional loop. The first functional loop includes a memory bank, a read interleaver, a first multiplexer (MUX), a RAM file, a log-MAP decoder, a write interleaver, and a second MUX. The disclosed turbo decoder further includes a second mode of operation in which a second functional loop is used. The second functional loop includes the memory bank, the first MUX, the RAM file, the log-MAP decoder, and the second MUX. The memory bank is a dual port extrinsic memory. The disclosed turbo decoder circuit switches between the first mode and the second mode.

摘要翻译： 一种高效的turbo解码器。 所公开的turbo解码器包括第一操作模式，其中turbo解码器使用第一功能回路。 第一功能循环包括存储体，读交织器，第一多路复用器（MUX），RAM文件，对数MAP解码器，写交织器和第二MUX。 所公开的turbo解码器还包括使用第二功能回路的第二操作模式。 第二功能循环包括存储体，第一MUX，RAM文件，log-MAP解码器和第二MUX。 存储器是双端口外部存储器。 所公开的turbo解码器电路在第一模式和第二模式之间切换。

公开(公告)号：US20030140304A1

公开(公告)日：2003-07-24

申请号：US10020532

申请日：2001-12-14

发明人： James Y. Hurt ,  Michael A. Howard ,  Robert J. Fuchs

IPC分类号： H03M013/03

CPC分类号： H04L1/005 ,  H03M13/235 ,  H03M13/275 ,  H03M13/2764 ,  H03M13/2903 ,  H03M13/2972 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6575 ,  H04L1/0043 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0069 ,  H04L1/0071

摘要： A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.

摘要翻译： 并行地编码多个比特的方法和装置，其中递归生成输出。 在每个时钟周期期间，编码器处理多个比特并且产生与常规卷积编码器中的多个时钟周期顺序生成的输出一致的输出。 在一个实施例中，输入数据存储在多个存储器存储单元中，然后每个存储单元被唯一地寻址以向并行编码器提供数据。

公开(公告)号：US20030066022A1

公开(公告)日：2003-04-03

申请号：US10252394

申请日：2002-09-24

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

IPC分类号： H03M013/03

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元; 对由指令取出单元取出的指令进行解码的解码单元，以及执行由解码单元解码的指令的执行单元。 执行单元包括将第一数据与第二数据进行比较的第一比较单元和将第三数据与第四数据进行比较的第二比较单元。 第一比较单元和第二比较单元并行操作。 此外，第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元分别在高阶位置和低位置输出任何两个新的路径度量。

公开(公告)号：US06477680B2

公开(公告)日：2002-11-05

申请号：US09105759

申请日：1998-06-26

申请人： Syed Aon Mujtaba

发明人： Syed Aon Mujtaba

IPC分类号： H03M1341

CPC分类号： H03M13/6563 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6577

摘要： A convolutional decoder for decoding received symbols in a communication system includes a branch metric calculator, and add-compare-select engine and a traceback unit. The branch metric calculator computes branch metrics for transitions in a trellis representative of a convolutional code used to generate the symbols. In accordance with the invention, the branch metrics are computed from an offset binary representation of the symbols using an inverse likelihood function, such that the resulting path metrics grow at a smaller rate and therefore require less memory. The add-compare-select engine processes path metrics generated from the branch metrics so as to determine a selected path through at least a portion of the trellis, and may utilize a state-serial architecture which computes path metrics for k states of a given stage of the trellis per clock cycle, using branch metrics obtained from k sets of registers in the branch metric calculator. The traceback unit generates a sequence of decoded bits from the selected path, and may be configured to include a staging register and a traceback memory. The staging register receives selected path information from the add-compare-select engine, and the contents of the staging register for a given stage of the trellis are loaded into the traceback memory when the staging register becomes full, at a location given by a number of the stage modulo a predetermined traceback length.

摘要翻译： 用于对通信系统中的接收符号进行解码的卷积解码器包括分支度量计算器和加法比较选择引擎和追溯单元。 分支度量计算器计算用于代表用于生成符号的卷积码的网格中的转变的分支度量。 根据本发明，使用逆似然函数从符号的偏移二进制表示中计算分支度量，使得所得到的路径度量以较小的速率增长，因此需要更少的存储器。 加法比选择引擎处理从分支度量产生的路径度量，以便确定通过网格的至少一部分的所选路径，并且可以利用状态 - 串行体系结构，其计算给定阶段的k个状态的路径度量 的每个时钟周期的网格，使用从分支度量计算器中的k组寄存器获得的分支度量。 回溯单元从所选择的路径生成解码比特序列，并且可以被配置为包括分段寄存器和回溯存储器。 分级寄存器从加法比较选择引擎接收所选择的路径信息，并且当分段寄存器变满时，在给定阶段的格架上的分段寄存器的内容被加载到追溯存储器中， 的阶段模数预定的追溯长度。

公开(公告)号：US20020010895A1

公开(公告)日：2002-01-24

申请号：US09105759

申请日：1998-06-26

发明人： SYED AON MUJTABA

IPC分类号： H03M013/03

CPC分类号： H03M13/6563 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6577

摘要： A convolutional decoder for decoding received symbols in a communication system includes a branch metric calculator, and add-compare-select engine and a traceback unit. The branch metric calculator computes branch metrics for transitions in a trellis representative of a convolutional code used to generate the symbols. In accordance with the invention, the branch metrics are computed from an offset binary representation of the symbols using an inverse likelihood function, such that the resulting path metrics grow at a smaller rate and therefore require less memory. The add-compare-select engine processes path metrics generated from the branch metrics so as to determine a selected path through at least a portion of the trellis, and may utilize a state-serial architecture which computes path metrics for k states of a given stage of the trellis per clock cycle, using branch metrics obtained from k sets of registers in the branch metric calculator. The traceback unit generates a sequence of decoded bits from the selected path, and may be configured to include a staging register and a traceback memory. The staging register receives selected path information from the add-compare-select engine, and the contents of the staging register for a given stage of the trellis are loaded into the traceback memory when the staging register becomes full, at a location given by a number of the stage modulo a predetermined traceback length.

摘要翻译： 用于对通信系统中的接收符号进行解码的卷积解码器包括分支度量计算器和加法比较选择引擎和追溯单元。 分支度量计算器计算用于代表用于生成符号的卷积码的网格中的转变的分支度量。 根据本发明，使用逆似然函数从符号的偏移二进制表示中计算分支度量，使得所得到的路径度量以较小的速率增长，因此需要更少的存储器。 加法比选择引擎处理从分支度量产生的路径度量，以便确定通过网格的至少一部分的所选路径，并且可以利用状态 - 串行体系结构，其计算给定阶段的k个状态的路径度量 的每个时钟周期的网格，使用从分支度量计算器中的k组寄存器获得的分支度量。 回溯单元从所选择的路径生成解码比特序列，并且可以被配置为包括分段寄存器和回溯存储器。 分级寄存器从加法比较选择引擎接收所选择的路径信息，并且当分段寄存器变满时，在给定阶段的格架上的分段寄存器的内容被加载到追溯存储器中， 的阶段模数预定的追溯长度。

公开(公告)号：US06263473B1

公开(公告)日：2001-07-17

申请号：US09494362

申请日：2000-01-31

申请人： Takehiro Kamada

发明人： Takehiro Kamada

IPC分类号： H03M1341

CPC分类号： H03M13/6502 ,  H03M13/41 ,  H03M13/4169 ,  H03M13/6505 ,  H03M13/6563

摘要： The present invention provides an improved Viterbi decoder with a trace-back memory that requires a much less storage capacity required for signal decoding processing as compared with a commonly-used trace-back memory. Based on an input received code, an add-compare-select (ACS) circuit generates path select (PS) signals, and m generated PS signals per unit are written into a path storing means and are fed to a starting node number deciding circuit where the number m indicates a trace-back length. The starting node number deciding circuit finds from the m PS signals a trace-back starting node number for a PS signal preceding the m PS signals. PS signals are read out from the path storing means, trace-back processing starts from the starting node number found by the starting node number deciding circuit, and signal decoding processing is carried out. This eliminates the need for providing a state of performing provisional trace-back processing for finding a starting node number, thereby reducing the number of states necessary for the decoding of signals from four down to three. This reduces the storage capacity of memory required for storing PS signals and thereby achieves a considerable reduction of the circuit size.

摘要翻译： 本发明提供了一种具有追溯存储器的改进的维特比解码器，其与常用的追溯存储器相比需要比信号解码处理所需的更少的存储容量。 基于输入接收的代码，加法比较选择（ACS）电路产生路径选择（PS）信号，并且每单位的m个生成的PS信号被写入路径存储装置，并被馈送到起始节点号决定电路， 数字m表示追溯长度。 起始节点号决定电路从m PS信号中找出用于m PS信号之前的PS信号的追溯起始节点号。 从路径存储装置读出PS信号，从起始节点号决定电路所发现的起始节点编号开始追踪处理，进行信号解码处理。 这消除了提供执行用于查找起始节点号码的临时追溯处理的状态的需要，从而减少了信号从4个到3个解码所需的状态数量。 这降低了存储PS信号所需的存储器的存储容量，从而实现了电路尺寸的显着降低。