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196 条记录 (耗时 0.013 秒)

    Direct-coupled triggered flip-flop
    61.
    发明授权
    Direct-coupled triggered flip-flop 失效
    直接耦合触发翻转

    公开(公告)号：US3767943A

    公开(公告)日：1973-10-23

    申请号：US3767943D

    申请日：1972-11-03

    申请人： RCA CORP

    发明人： STECKLER S

    IPC分类号： H03K3/288 ,  H03K3/286

    CPC分类号： H03K3/288

    摘要： Each of first and second grounded-emitter amplifier transistors has a diode connected between its collector electrode and the base electrode of the other to provide a storage flip-flop. Third and fourth transistors have collector electrodes, each coupled to a source of triggering pulses by similar resistors; cross-coupled collector and base electrodes; and emitter electrodes, each connected to a separate one of the base electrodes of the first and second transistors and each connected to ground reference potential by a resistor. So connected, the third and fourth transistors provide a commutating flip-flop, functioning as a steering network for trigger pulses and providing for short term memory of the previous state of the storage flip during its transition in response to a triggering impulse. The use of diodes to cross-couple the collector and base electrodes of the first and second transistors in the storage flip-flop permits fast transitions of the storage flip-flop despite the use of pinch resistor collector loads for the first, second, third and fourth transistors and restricted amplitude triggering pulses, which are employed to reduce power consumption of the direct-coupled triggered flip-flop.

    摘要翻译： 第一和第二接地发射极放大器晶体管中的每一个具有连接在其集电极和另一个的基极之间的二极管，以提供存储触发器。 第三和第四晶体管具有集电极，每个都通过类似的电阻耦合到触发脉冲源; 交叉耦合集电极和基极; 和发射极电极，每个发射极电极连接到第一和第二晶体管的基本电极的单独一个，并且各自通过电阻器连接到接地参考电位。 因此，第三和第四晶体管提供换向触发器，其作为用于触发脉冲的转向网络，并且响应于触发脉冲提供存储翻转的先前状态的短期存储。 使用二极管将存储触发器中的第一和第二晶体管的集电极和基极电极交叉耦合允许存储触发器的快速转变，尽管对于第一，第二，第三和第三晶体管使用夹持电阻器集电极负载， 第四晶体管和受限幅度触发脉冲，用于降低直接耦合触发触发器的功耗。

    Active element memory
    62.
    发明授权
    Active element memory 失效
    主动元件存储器

    公开(公告)号：US3764825A

    公开(公告)日：1973-10-09

    申请号：US3764825D

    申请日：1972-01-10

    申请人： STEWART R

    发明人： STEWART R

    IPC分类号： G11C7/20 ,  G11C11/411 ,  G11C14/00 ,  G11C17/08 ,  H03K3/286 ,  H03K3/288 ,  H03K17/22 ,  G11C11/40

    CPC分类号： H03K3/288 ,  G11C7/20 ,  G11C11/4116 ,  G11C14/00 ,  G11C17/08 ,  H03K3/2865 ,  H03K17/22 ,  H03K2017/226

    摘要： Bistable memory elements having a pair of active transistor components are provided with separate voltage supply lines. The collector and/or emitter circuits of each transistor pair are selectively connected to different ones of the voltage supply lines, which are actuated in sequence to set each memory element into a predetermined initial state, thus combining the advantages of read-only operation with random access capabilities.

    摘要翻译： 具有一对有源晶体管组件的双稳态存储元件设置有单独的电压供应线。 每个晶体管对的集电极和/或发射极电路选择性地连接到不同的电压供给线，这些电压供应线被依次致动以将每个存储元件设置为预定的初始状态，从而将只读操作的优点与随机 访问功能。

    Integrated bistable circuit
    63.
    发明授权
    Integrated bistable circuit 失效
    集成式双电路

    公开(公告)号：US3700929A

    公开(公告)日：1972-10-24

    申请号：US3700929D

    申请日：1972-01-10

    申请人： MOTOROLA INC

    发明人： FREDERIKSEN THOMAS M

    IPC分类号： H03K3/288 ,  H03K3/286

    CPC分类号： H03K3/288

    摘要： A protected monolithic integrated flip-flop circuit comprises a pair of NPN transistors as the active flip-flop elements with the collectors of each of these transistors being supplied from a constant current source in the form of a dual-collector lateral PNP transistor. Collector-to-substrate distributed capacitance operates to retard the switching time of the flip-flop causing it to be a low speed flip-flop. A pair of substrate PNP transistors are used to apply the input trigger signals to the NPN transistors and operate to provide protection for the circuit against high positive or negative input voltages.

    摘要翻译： 受保护的单片集成触发器电路包括一对NPN晶体管作为有源触发器元件，其中这些晶体管的集电极由双集电极横向PNP晶体管形式的恒流源提供。 集电极到衬底的分布电容用于延迟触发器的开关时间，使其成为低速触发器。 使用一对衬底PNP晶体管将输入触发信号施加到NPN晶体管，并且操作以为电路提供保护以防止高的正或负输入电压。

    Circuit for providing nonvolatile memory
    64.
    发明授权
    Circuit for providing nonvolatile memory 失效
    提供非易失性存储器的电路

    公开(公告)号：US3558912A

    公开(公告)日：1971-01-26

    申请号：US3558912D

    申请日：1968-08-22

    申请人： US AIR FORCE

    发明人： SPALL EDWARD J

    IPC分类号： H02H7/20 ,  H03K3/288

    CPC分类号： H02H7/20 ,  H03K3/288

    摘要： A bistable flip-flop circuit having a memory core is designed to return to a preferred state after power failure or radiation burst. A feedback loop from the memory core senses whether the preferred state is the same as the state before power failure or radiation and, if not the same, changes the state of the flipflop circuit.