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公开(公告)号：US09746863B2
公开(公告)日：2017-08-29
申请号：US14960052
申请日：2015-12-04
Applicant: STMicroelectronics SA
Inventor： Philippe Galy , Sotirios Athanasiou , Julien Le Coz , Sylvain Engels
CPC classification number: G05F1/463 , H01L23/345 , H01L27/0251 , H01L27/0629 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.
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公开(公告)号：US20170236923A1
公开(公告)日：2017-08-17
申请号：US15221051
申请日：2016-07-27
Applicant: STMicroelectronics SA
Inventor： Pascal Chevalier
IPC: H01L29/732 , H01L29/66 , H01L21/308 , H01L29/08 , H01L29/10
CPC classification number: H01L29/732 , H01L21/308 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/7371
Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.
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773.发明申请
公开(公告)号：US20170236753A1
公开(公告)日：2017-08-17
申请号：US15583342
申请日：2017-05-01
Applicant: STMicroelectronics SA
Inventor： Sylvain Joblot , Pierre Bar
IPC: H01L21/768 , H01P11/00 , H01L23/66 , H01L21/48 , H01L21/762
CPC classification number: H01L21/76831 , G02B6/12 , H01L21/4846 , H01L21/76224 , H01L21/76898 , H01L23/66 , H01P11/003
Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
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公开(公告)号：US20170230014A1
公开(公告)日：2017-08-10
申请号：US15229464
申请日：2016-08-05
Applicant: STMicroelectronics SA
Inventor： Raphael Paulin
CPC classification number: H03F1/565 , H03F1/086 , H03F1/223 , H03F3/195 , H03F2200/108 , H03F2200/181 , H03F2200/216 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/321 , H03F2200/336 , H03F2200/387 , H03F2200/391 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/75 , H04B5/0081
Abstract: A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.
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公开(公告)号：US09711550B2
公开(公告)日：2017-07-18
申请号：US14840680
申请日：2015-08-31
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Laurent Favennec , Didier Dutartre , Francois Roy
IPC: H01L27/146 , H01L31/11 , H01L31/18
CPC classification number: H01L27/1462 , H01L27/1461 , H01L27/14612 , H01L27/1463 , H01L27/14685 , H01L27/14689 , H01L31/11 , H01L31/1804 , Y02E10/547 , Y02P70/521
Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.
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公开(公告)号：US09691871B1
公开(公告)日：2017-06-27
申请号：US14973825
申请日：2015-12-18
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： Pierre Caubet , Florian Domengie , Carlos Augusto Suarez Segovia , Aurelie Bajolet , Onintza Ros Bengoechea
CPC classification number: H01L21/28088 , H01L29/4966
Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
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公开(公告)号：US09673329B2
公开(公告)日：2017-06-06
申请号：US14959430
申请日：2015-12-04
Inventor： Yves Morand , Romain Wacquez , Laurent Grenouillet , Yannick Le Tiec , Maud Vinet
CPC classification number: H01L29/785 , H01L27/1211 , H01L29/0649 , H01L29/0657 , H01L29/66795 , H01L29/66818 , H01L29/7856
Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.
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公开(公告)号：US20170148780A1
公开(公告)日：2017-05-25
申请号：US15096975
申请日：2016-04-12
Applicant: STMicroelectronics SA
Inventor： Johan Bourgeat , Jean Jimenez
IPC: H01L27/02 , H01L29/744 , H01L29/10 , H01L29/74
CPC classification number: H01L27/0251 , H01L27/0262 , H01L29/1095 , H01L29/7436 , H01L29/744
Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
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公开(公告)号：US09646914B2
公开(公告)日：2017-05-09
申请号：US14958623
申请日：2015-12-03
Applicant: STMicroelectronics SA
Inventor： Pierre Bar , Perceval Coudrain
IPC: H01L23/52 , H01L23/373 , H01L21/48 , H01L23/498 , H01L23/473 , H01L23/48 , H01L25/065 , H01L25/00
CPC classification number: H01L23/373 , H01L21/4846 , H01L21/486 , H01L21/4882 , H01L21/76898 , H01L23/473 , H01L23/481 , H01L23/498 , H01L23/49827 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589
Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.
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公开(公告)号：US09645469B2
公开(公告)日：2017-05-09
申请号：US14836011
申请日：2015-08-26
Applicant: STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor： Patrick Lemaitre , Jean-Francois Carpentier , Charles Baudot , Jean-Robert Manouvrier
CPC classification number: G02F1/225 , G02F1/025 , G02F1/2257 , G02F2001/212 , G02F2203/15
Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.
