公开(公告)号：US09196534B2

公开(公告)日：2015-11-24

申请号：US13775212

申请日：2013-02-24

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yan Xun Xue ,  Ping Huang ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Lei Shi ,  Liang Zhao ,  Ping Li Wu ,  Lei Duan ,  Yuping Gong

IPC: H01L21/02 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/1184 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Abstract translation: 一种用于在倒装芯片工艺中制备半导体器件的方法包括形成围绕每个半导体芯片的深槽; 沉积第一塑料封装材料以形成覆盖半导体晶片的前表面并填充深槽的第一塑料封装层; 在研磨后在半导体晶片的背面沉积金属层; 研磨金属层的最外部分，从而形成位于未被金属层覆盖的半导体晶片的边缘周围的背面的环形区域; 沿着由填充有第一塑料包装材料的每个深槽的两端形成的直线切割填充在深槽中的第一塑料封装层，半导体晶片，金属层和第一塑料封装材料; 并且拾取半导体器件并安装在衬底上，而不会翻转半导体器件。

公开(公告)号：US09190478B2

公开(公告)日：2015-11-17

申请号：US14138103

申请日：2013-12-22

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Daniel Calafut ,  Madhur Bobde ,  Yeeheng Lee ,  Hong Chang

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42368 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A method for forming a dual oxide thickness trench gate structure for a power MOSFET includes providing a semiconductor substrate; forming a first trench on a top surface of the substrate; forming a first oxide layer in the first trench where the first oxide layer has a first depth from the bottom of the first trench; forming a dielectric spacer along the sidewall of the first trench and on the first oxide layer; etching the first oxide layer exposed by the dielectric spacer to a second depth from the bottom of the first trench using the dielectric spacer as a mask where the second depth is lower than the first depth; removing the dielectric spacer; and forming a second oxide layer along the sidewall of the first trench above the first oxide layer where the second oxide layer has a thickness thinner than the thickness of the first oxide layer.

Abstract translation: 用于形成用于功率MOSFET的双重氧化物厚度沟槽栅极结构的方法包括提供半导体衬底; 在所述基板的顶表面上形成第一沟槽; 在所述第一沟槽中形成第一氧化物层，其中所述第一氧化物层具有从所述第一沟槽的底部开始的第一深度; 沿着所述第一沟槽的侧壁和所述第一氧化物层形成电介质间隔物; 使用所述电介质间隔物作为所述第二深度低于所述第一深度的掩模，将由所述电介质间隔物暴露的所述第一氧化物层蚀刻到所述第一沟槽的底部的第二深度; 去除介电间隔物; 以及沿着所述第一氧化物层的所述第一沟槽的所述侧壁形成第二氧化物层，其中所述第二氧化物层具有比所述第一氧化物层的厚度更薄的厚度。

公开(公告)号：US09165866B2

公开(公告)日：2015-10-20

申请号：US14071626

申请日：2013-11-04

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC: H01L23/495 ,  H01L23/02 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Abstract translation: 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20150279989A1

公开(公告)日：2015-10-01

申请号：US14736197

申请日：2015-06-10

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Madhur Bobde ,  Hamza Yilmaz ,  Daniel Calafut ,  Karthik Padmanabhan

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/02164 ,  H01L21/26586 ,  H01L21/28035 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7832 ,  H01L29/8083

Abstract: In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies.

Abstract translation: 在一些实施例中，通常在高压开关器件（“通常在开关器件”上）结合有沟槽栅极端子和掩埋掺杂栅极区域。 在其它实施例中，通常在高压开关器件上控制的表面栅极形成有沟槽结构并且包括由表面栅电极控制的表面通道。 在开关器件上正常控制的表面栅可以进一步并入沟槽栅极电极和掩埋掺杂栅极区域以耗尽导电沟道以帮助关断正常开关器件。 如此构造的正常开关器件可以容易地与MOSFET器件集成并且使用现有的高压MOSFET制造技术形成。

公开(公告)号：US09147586B2

公开(公告)日：2015-09-29

申请号：US14083452

申请日：2013-11-19

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Jun Lu ,  Kai Liu ,  Yan Xun Xue

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L25/07 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract translation: 具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。 制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅 切割或磨削。

公开(公告)号：US09136380B2

公开(公告)日：2015-09-15

申请号：US14329806

申请日：2014-07-11

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与沿着栅极盖的侧壁形成的间隔物自对准。 另外，有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 与自对准源触点结合的两步栅极氧化物允许生产具有深亚微米级的间距的器件。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US09136370B2

公开(公告)日：2015-09-15

申请号：US14294520

申请日：2014-06-03

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Sik Lui ,  Yi Su ,  Daniel Ng ,  Daniel Calafut ,  Anup Bhalla

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L23/64 ,  H01L29/423 ,  H01L23/00

CPC classification number: H01L29/7813 ,  H01L23/647 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2224/0603 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead.

Abstract translation: 形成在体层中的沟槽和衬底的外延层衬有介电层。 形成在沟槽下部的屏蔽电极被电介质层绝缘。 形成在屏蔽电极上方的沟槽中的栅电极通过另一介质层与屏蔽电极绝缘。 形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。 形成在主体层上方的源极焊盘电连接到源极区域并与栅电极和屏蔽电极绝缘。 源极焊盘提供与源极区域的外部接触。 栅极焊盘提供与栅电极的外部接触。 屏蔽电极焊盘提供与屏蔽电极的外部接触。 电阻元件电连接在屏蔽电极焊盘和源极之间。

公开(公告)号：US20150236005A1

公开(公告)日：2015-08-20

申请号：US14702690

申请日：2015-05-02

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Peter Wilson ,  Yan Huo ,  Zhiqiang Niu ,  Ming-Chen Lu

IPC: H01L25/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73104 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract translation: 一种混合封装多芯片半导体器件，包括引线框单元，第一半导体芯片，第二半导体芯片，第一互连结构和第二互连结构，其中第一半导体芯片附接在第一裸片上，第二半导体 芯片被翻转并附接在第三引脚和第二管芯焊盘上，第一互连结构电连接第一半导体芯片的前表面处的第一电极和第二半导体芯片的后表面处的第三电极和第二电极 在第一半导体芯片的前表面通过第二互连结构电连接。

公开(公告)号：US20150228729A1

公开(公告)日：2015-08-13

申请号：US14632352

申请日：2015-02-26

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-Se Ho

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/872 ,  H01L29/861

CPC classification number: H01L29/872 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/28581 ,  H01L21/30612 ,  H01L21/31111 ,  H01L21/56 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/18 ,  H01L27/0248 ,  H01L27/0814 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05016 ,  H01L2224/05567 ,  H01L2224/11616 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode.

Abstract translation: 电路包括并联连接的垂直导电氮化镓基肖特基二极管和垂直导电硅基PN结二极管。 肖特基二极管和PN结二极管封装在相同的半导体封装中，并且PN结二极管不响应肖特基二极管正向偏置而导通。 在一些实施例中，硅基PN结二极管的击穿电压低于基于氮化镓的肖特基二极管的击穿电压。 基于硅的PN结二极管响应于反向偏置的氮化镓基肖特基二极管进入击穿，以将反向偏置雪崩电流转移离开基于氮化镓的肖特基二极管。

公开(公告)号：US09106075B2

公开(公告)日：2015-08-11

申请号：US13950146

申请日：2013-07-24

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Mark Tomas ,  Zhiye Zhang ,  Allen Chang ,  Kuang Ming Chang ,  Gilbert Lee

IPC: H02M3/335 ,  H02H7/122 ,  H02M3/158 ,  H02M1/00 ,  H02H9/02

CPC classification number: H02M1/32 ,  H02H7/1225 ,  H02H9/02 ,  H02M3/1584 ,  H02M2001/0009

Abstract: A fault tolerant power supply system includes at least one load switch configured to connect an input voltage to an output node of the load switch when the load switch is turned on and at least one power channel coupled to the load switch to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the low-side power switch, to determine that the current flowing through the low-side power switch has exceeded a current limit threshold, and to disable the low-side power switch and the load switch in response to the determination that the current flowing in the low-side power switch has exceeded the current limit threshold.

Abstract translation: 容错电源系统包括至少一个负载开关，其被配置为当负载开关接通时将输入电压连接到负载开关的输出节点，以及耦合到负载开关的至少一个电力通道以接收输入电压。 功率通道被配置为降压转换器，并且至少包括高侧电源开关和低侧电源开关。 容错电源系统被配置为测量流过低端电源开关的电流，以确定流过低压侧电源开关的电流已经超过限流阈值，并禁用低端电源开关 以及负载开关响应于在低侧电源开关中流动的电流已经超过电流限制阈值的确定。