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119 条记录 (耗时 0.037 秒)

    Apparatus and method for detecting over-programming condition in multistate memory device
    72.
    发明授权
    Apparatus and method for detecting over-programming condition in multistate memory device 失效
    多状态存储器件中过度编程条件的检测装置及方法

    公开(公告)号：US07457997B2

    公开(公告)日：2008-11-25

    申请号：US10629279

    申请日：2003-07-29

    申请人： Robert D. Norman ,  Christophe J. Chevallier

    发明人： Robert D. Norman ,  Christophe J. Chevallier

    IPC分类号： G11C29/00 ,  G11C16/06 ,  G11C16/04 ,  G11C7/00

    CPC分类号： G11C29/765 ,  G06F11/1072 ,  G11C7/1039 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3463 ,  G11C29/00 ,  G11C29/52 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2211/5643

    摘要： An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

    摘要翻译： 一种用于检测多态存储器单元中的过编程状态的装置和方法。 本发明还涉及识别过程编程的单元并提供写入用于过程编程单元的数据的备用位置。 当发现包含在多状态存储器单元中的数据相对于其预期编程（阈值电压电平）状态被发现过度编程时，过程编程状态检测电路产生错误信号。 在检测到过度编程的单元时，修改存储器系统的编程操作以中止对单元的进一步编程尝试。 过度编程状态检测电路还用于帮助校正过度编程状态，允许由存储器系统补偿编程错误。

    Method and system for arbitrating priority bids sent over serial links to a multi-port storage device
    73.
    发明授权
    Method and system for arbitrating priority bids sent over serial links to a multi-port storage device 有权
    仲裁通过串行链路发送到多端口存储设备的优先级投标的方法和系统

    公开(公告)号：US07171525B1

    公开(公告)日：2007-01-30

    申请号：US10210839

    申请日：2002-07-31

    申请人： Robert D. Norman ,  Frank Sai-Keung Lee

    发明人： Robert D. Norman ,  Frank Sai-Keung Lee

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0659 ,  G06F3/0622 ,  G06F3/0689

    摘要： A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between its ports and the operational portion. In response to a set of competing priority bids from the users, the arbitration circuitry grants one bid (including by sending an acknowledgement to the successful bidder) and preferably holds each non-granted competing bid without sending any notification to the unsuccessful bidder until the successful bidder sends a deselect signal. The system can be a RAID system including at least two disk drives and at least two controllers, where at least one drive is a multi-port device shared by at least two of the controllers. Preferably, each priority bid and deselect signal is a primitive code (e.g., an ordered sequence of a 10-bit control character and three 10-bit data characters in SATA format). Other aspects of the invention are multi-port storage devices and users for use in such a system.

    摘要翻译： 一种包括多端口存储设备（例如，磁盘驱动器）和至少两个用户的系统，每个用户通过串行链路耦合到存储设备的端口。 存储装置在其端口和操作部分之间具有操作部分和接口（包括仲裁电路）。 为响应来自用户的一组竞争优先权投标，仲裁电路授予一个投标（包括通过向中标者发送确认），并且优选地保持每个未被许可的竞争投标，而不向不成功的投标人发送任何通知，直到成功 投标人发送取消信号。 该系统可以是包括至少两个磁盘驱动器和至少两个控制器的RAID系统，其中至少一个驱动器是由至少两个控制器共享的多端口设备。 优选地，每个优先权出价和取消选择信号是原始码（例如，10位控制字符的有序序列和SATA格式的三个10位数据字符）。 本发明的其他方面是用于这种系统的多端口存储设备和用户。

    Systems and methods for self-calibration
    74.
    发明授权
    Systems and methods for self-calibration 有权
    用于自校准的系统和方法

    公开(公告)号：US06850125B2

    公开(公告)日：2005-02-01

    申请号：US09930828

    申请日：2001-08-15

    申请人： Robert D Norman ,  Dominik J. Schmidt

    发明人： Robert D Norman ,  Dominik J. Schmidt

    IPC分类号： G01K15/00 ,  G05D23/24 ,  H03L1/00 ,  H03B5/04

    CPC分类号： H04Q9/00 ,  G01K15/00 ,  G05D23/1917 ,  G05D23/24 ,  H03L1/00

    摘要： A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.

    摘要翻译： 自校准集成电路包括具有与处理器一起使用的至少一个模拟功能的处理器; 适于感测所述至少一个模拟功能的一个或多个环境参数的一个或多个传感器; 以及固态存储器，其被配置为存储所述至少一个模拟功能的所述一个或多个环境参数。

    Apparatus and method for reducing programming cycles for multistate memory system
    75.
    发明授权
    Apparatus and method for reducing programming cycles for multistate memory system 失效
    用于减少多状态存储器系统的编程周期的装置和方法

    公开(公告)号：US06826649B2

    公开(公告)日：2004-11-30

    申请号：US10755538

    申请日：2004-01-12

    申请人： Robert D. Norman

    发明人： Robert D. Norman

    IPC分类号： G06F1200

    CPC分类号： G11C11/5628 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5647 ,  Y10T74/18928

    摘要： A method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. The invention first determines the average programming state (corresponding to an average threshold voltage level) for the set of data which is to be programmed into the memory cells. This is accomplished by counting the number of programming states which must be traversed in programming the cells with the data. If the majority of the data requires programming the memory cell(s) to the upper two programming states (in the case of a two bit per cell or four state system), then the data is inverted and stored in the memory in the inverted form. This reduces the amount of programming time, the number of programming states traversed, and the power consumed in programming the memory cell(s) with the data field.

    摘要翻译： 一种用于给具有给定的数据集的多组存储单元进行编程时减少编程状态（阈值电压电平）数量的方法。 本发明首先确定要编程到存储器单元中的数据组的平均编程状态（对应于平均阈值电压电平）。 这是通过对使用数据编程单元格中必须遍历的编程状态数进行计数来实现的。 如果大多数数据需要将存储器单元编程到上两个编程状态（在每个单元或四个状态系统为2位的情况下），则数据被反转并以倒置形式存储在存储器中 。 这减少了编程时间的数量，遍历的编程状态的数量以及使用数据字段编程存储单元的功耗。

    Memory system having flexible bus structure and method
    79.
    发明授权
    Memory system having flexible bus structure and method 有权
    具有灵活总线结构和方法的存储系统

    公开(公告)号：US06320815B1

    公开(公告)日：2001-11-20

    申请号：US09711623

    申请日：2000-11-13

    申请人： Robert D. Norman ,  Vinod C. Lakhani ,  Christophe J. Chevallier

    发明人： Robert D. Norman ,  Vinod C. Lakhani ,  Christophe J. Chevallier

    IPC分类号： G11C800

    CPC分类号： G06F12/0661

    摘要： A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.

    摘要翻译： 一种具有通过系统总线连接到多个存储器件的存储器控​​制器的存储器系统。 存储器控制器通过系统总线向存储器件发出器件选择，存储器程序和存储器读取指令，器件选择指令包括器件选择地址和器件选择命令。 存储器件各自包括存储器单元阵列和用于对阵列执行存储器读取和编程操作的存储器操作管理器。 存储器操作管理器包括地址比较器，其将系统总线上接收的设备选择地址与存储在存储设备中的本地地址进行比较，以及命令解码器，其用于检测系统总线上的命令，存储器操作管理器操作以切换存储器 设备从设备禁用状态到启用设备的状态，当存储设备接收与本地地址匹配的选择地址以及设备选择命令之一时。

    Device and method for controlling solid-state memory system
    80.
    发明授权
    Device and method for controlling solid-state memory system 失效
    用于控制固态存储器系统的装置和方法

    公开(公告)号：US06317812B1

    公开(公告)日：2001-11-13

    申请号：US09657369

    申请日：2000-09-08

    申请人： Karl M. J. Lofgren ,  Jeffrey Donald Stai ,  Anil Gupta ,  Robert D. Norman ,  Sanjay Mehrotra

    发明人： Karl M. J. Lofgren ,  Jeffrey Donald Stai ,  Anil Gupta ,  Robert D. Norman ,  Sanjay Mehrotra

    IPC分类号： G06F1200

    CPC分类号： G11C5/04 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0676 ,  G06F13/1668 ,  G06F13/4243 ,  G11C5/00 ,  G11C5/066 ,  G11C8/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

    摘要翻译： 存储器系统包括固态存储器件阵列，其经由具有极少线路的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。 命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。 序列化信息伴随着一个控制信号，以帮助整理复用的组件。 阵列中的每个内存设备都由阵列装载分配一个阵列地址。 通过在设备总线上广播的适当地址来选择存储设备，而不需要通常的专用选择信号。 保留阵列安装配置用于无条件地选择安装的设备。 通过设备总线广播的保留地址将取消所有先前选择的存储设备。 通过读取流技术增强读取性能，其中当当前大量数据被序列化并从存储器子系统移出到控制器模块时，控制器模块还设置下一个数据块的地址以开始 寻址内存系统。