摘要:
A semiconductor memory device having a plurality of banks of memory cells is provided. The device has a data line provided in each of the banks for coupling to one of the memory cells in the corresponding bank. A common data line is shared by the banks, and is selectively coupled to one of the data lines through switches. Additionally, an amplifier is coupled to the common data line to amplify data read from a selected memory cell, and an I/O line is coupled to the amplifier to transmit the amplified data to an outer section. In the device, one of the banks of memory cells is selected by a bank select signal. Therefore, the amplifier is shared by the banks. Further the length of the I/O line can be shortened so that the load on the amplifier can be reduced. Accordingly, chip area is decreased and the speed of the memory device is improved.
摘要:
The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit normally comprising a counter constitutes a shift register in a column addressing circuit at a preceding stage of a column address buffer so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.
摘要:
A semiconductor integrated circuit includes a rectangular semiconductor chip having a main surface, a plurality of pads formed in a peripheral portion of the main surface of the semiconductor chip, for connection to external connecting members, a plurality of circuit elements of an integrated circuit formed in an area of the main surface other than an area in which the plurality of pads are formed, and at least one characteristic evaluating circuit element connected to at least one of the plurality of circuit elements of the integrated circuit by sharing an impurity doped region which forms part of the at least one circuit element with the at least one circuit element of the integrated circuit in an area of the main surface other than the peripheral portion in which the plurality of pads are formed.
摘要:
A semiconductor memory device includes a first power source having a non-ground potential V.sub.cc1 terminal and a ground potential V.sub.ss1 terminal. The internal circuit is supplied with power from the first power source. The first power source is dedicated to the internal circuit. The internal circuit selects a memory cell of a memory cell array in accordance with an inputted address. The internal circuit has a first output terminal and a second output terminal the first output terminal outputs one of a pair of potential V.sub.cc1 and V.sub.ss1 and the second output terminal outputs the other of the pair in accordance with the data in the selected memory cell. A second power source has a non-ground potential V.sub.cc2 terminal and a ground potential V.sub.ss2 terminal. The output circuit is supplied with power from the second power source which is dedicated to the output circuit. The output circuit has first and second transistors serially connected between the V.sub.cc2 terminal and V.sub.ss2. The control terminals of the first and second transistors are connected to the first and second output terminals. A third transistor is connected between an interconnection between the first and second transistors connected to a data output from which data is externally outputted and the first output terminal, and the control terminal of the third transistor being connected to the second output terminal.
摘要:
In the semiconductor memory composed of divided dynamic memory cell arrays, when a drive signal is supplied to a word line selected by a row decoder, data stored at the memory cells connected to the word line are transferred to bit lines, respectively. A change in potential at the bit line pair is amplified by the sense amplifier to completely read the data. To prevent the bit line pairs from being sensed erroneously due to fluctuation of the timings at which the word line driving signals are generated in the divided cell arrays, a bit line sense signal is generated a predetermined delay time after all the word line driving signals have been generated, in order to drive all the sense amplifiers simultaneously, so that data can be definitely read from the memory cells to the bit lines. To detect that all the word line driving signals have been generated, a drive signal detection section is connected between word line driving circuits for all the divided cell arrays and a delay circuit connected to a sense amplifier driving circuit.
摘要:
In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.
摘要:
A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, registers and a control unit. The control unit allows the write operational mode of the column decoder to switch. In the ordinary write operational mode, data in the n registers are written into the active memory cells of the n memory cell columns in on column block selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2.sup.N column blocks selected by the column decoder, respectively. Another semiconductor memory device comprises N memory units. Each memory unit comprises a memory cell array, a row decoder, a first column decoder, a second column decoder, a data input terminal, registers and a control circuit. The control circuit is operative to allow the operational mode. When the device is in the ordinary mode, data latched in the register is written into one memory cell connected to one word line selected by the row decoder of one column selected by the first column decoder of column blocks selected by the second decoder. While when the device is in the block write mode, data latched in the register is written at the same time into j memory cells connected to one word line selected by the row decoder of column blocks selected by the second column decoder.
摘要:
A semiconductor memory device is disclosed which comprises, as shown in FIG. 1, a pair of column lines, memory cells connected to the corresponding column lines, a sense amplifier connected to the column lines, row lines for selecting the memory cells in accordance with a row address signal, and first and second transistors having their current paths connected between the column lines and a fixed potential supply terminal supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors are connected to the first and second row lines for a data rewrite operation which can be selected independently of the row line.
摘要:
An integrated circuit includes an input buffer circuit and an output buffer circuit. The source voltage to the input buffer circuit and the output buffer circuit are supplied through bonding pads formed independently on a semiconductor chip, and electrically connected to a source potential lead pin. The input node of the input buffer circuit is coupled to the source potential of the output buffer circuit with a capacitor.