公开(公告)号：US20100067305A1

公开(公告)日：2010-03-18

申请号：US12509612

申请日：2009-07-27

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

IPC: G11C16/04 ,  G11C5/14

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.

Abstract translation: 公开了闪存和编程方法。 闪速存储器包括存储单元阵列，该存储单元阵列具有布置在包括所选择的字线和多个未选择的字线和多个位线的多个字线中的存储器单元，高电压发生器产生施加到该字线的编程电压 所选择的字线和施加到与所选字线相邻的未选择的字线中的至少一个的通过电压，以及控制逻辑，以控制编程电压的产生，使得编程电压在编程操作期间递增地增加 ，并产生通过电压，使得编程电压递增地增加。

公开(公告)号：US20100002523A1

公开(公告)日：2010-01-07

申请号：US12558717

申请日：2009-09-14

Applicant: Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/344 ,  G11C16/3454

Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

Abstract translation: 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

公开(公告)号：US20090213652A1

公开(公告)日：2009-08-27

申请号：US12264353

申请日：2008-11-04

Applicant: Ki-tae PARK ,  Yeong-taek LEE

Inventor： Ki-tae PARK ,  Yeong-taek LEE

IPC: G11C16/00 ,  G11C16/06

CPC classification number: G11C16/3418

Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

Abstract translation: 提供了一种对非易失性存储器件进行编程的方法。 该方法包括将第一编程脉冲施加到非易失性存储器件的对应字线，向第二编程脉冲施加第二编程脉冲，其中第二编程脉冲的电压与第一编程脉冲的电压不同，并施加电压 对于连接到字线的每个位线，施加到每个位线的电压根据要响应于第一编程脉冲或第二编程脉冲被编程到相应存储器单元的多个位值而彼此不同。

公开(公告)号：US20090207666A1

公开(公告)日：2009-08-20

申请号：US12428062

申请日：2009-04-22

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C16/349 ,  G11C16/3495

Abstract: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

Abstract translation: 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

公开(公告)号：US20090185422A1

公开(公告)日：2009-07-23

申请号：US12320003

申请日：2009-01-14

Applicant: Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

Inventor： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

IPC: G11C16/04 ,  G11C7/00 ,  G11C17/16 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/3427 ,  G11C17/16 ,  G11C29/52

Abstract: A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

Abstract translation: 闪存器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块的行解码器和第二存储单元阵列块。 存储单元阵列块。 行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号 存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

公开(公告)号：US20090180323A1

公开(公告)日：2009-07-16

申请号：US12320092

申请日：2009-01-16

Applicant: Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/04 ,  G11C8/00 ,  G11C16/06

CPC classification number: G11C16/10

Abstract: A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information.

Abstract translation: 非易失性存储器件可以包括适于存储指示尾部位存储器单元的尾部位标志信息的存储单元阵列，以及用于校准正常存储单元的程序启动电压和尾部程序启动电压的尾位控制器 - 位存储单元独立地基于尾位标志信息。

公开(公告)号：US07518909B2

公开(公告)日：2009-04-14

申请号：US11606908

申请日：2006-12-01

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.

Abstract translation: 非挥发性半导体存储器件包括第一和第二子存储器阵列和布置在第一和第二子存储器阵列之间的捆扎线。 通过同时向连接到第一子存储器阵列内的存储单元的奇偶位线施加编程电压来执行第一子存储器阵列的编程操作。

公开(公告)号：US20080316818A1

公开(公告)日：2008-12-25

申请号：US12141737

申请日：2008-06-18

Applicant: Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

IPC: G11C16/06

CPC classification number: G11C16/3418

Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

Abstract translation: 一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压 操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。 第二通过电压大于第一通过电压。

公开(公告)号：US07388798B2

公开(公告)日：2008-06-17

申请号：US11509991

申请日：2006-08-25

Applicant: Jin-Young Kim ,  Yeong-Taek Lee

Inventor： Jin-Young Kim ,  Yeong-Taek Lee

IPC: G11C7/02

CPC classification number: G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2211/4016

Abstract: A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines and second memory cells connected between a second bit line and second word lines; and a reference memory cell array block including first reference memory cells connected between a first reference bit line connected to the first bit line and a first reference word line and second reference memory cells connected between a second reference bit line connected to the second bit line and a second reference word line. When the first word lines are selected, the second reference memory cells are selected, and when the second word lines are selected, the first reference memory cells are selected. Thus, each bit line includes a reference memory cell and outputs reference signal from the reference memory cell so that data can be precisely sensed during a read operation.

Abstract translation: 包括没有电容器的存储单元的半导体存储器件包括：存储单元阵列块，包括连接在第一位线和第一字线之间的第一存储器单元和连接在第二位线和第二字线之间的第二存储器单元; 以及参考存储单元阵列块，其包括连接在与第一位线连接的第一参考位线和第一参考字线之间的第一参考存储单元，以及连接在与第二位线连接的第二参考位线之间的第二参考存储单元;以及 第二个参考字线。 当选择第一字线时，选择第二参考存储单元，并且当选择第二字线时，选择第一参考存储单元。 因此，每个位线包括参考存储单元并输出来自参考存储单元的参考信号，从而可以在读取操作期间精确地感测数据。

公开(公告)号：US07317646B2

公开(公告)日：2008-01-08

申请号：US11300009

申请日：2005-12-13

Applicant: Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Yeong-Taek Lee ,  Chul Lee

Inventor： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Yeong-Taek Lee ,  Chul Lee

IPC: G11C7/00

CPC classification number: G11C11/4097 ,  G11C2207/005

Abstract: Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.

Abstract translation: 提供了具有共享开放位线读出放大器架构的存储器件。 存储器件包括存储器单元阵列，每个存储单元阵列包括位线，以及读出放大器，配置为将至少两个位线耦合到存储单元阵列并被配置为耦合到不同存储单元阵列的至少两个位线。