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102 条记录 (耗时 0.034 秒)

    Scalable virtual appliance cloud (SVAC) and devices usable in an SVAC
    71.
    发明授权
    Scalable virtual appliance cloud (SVAC) and devices usable in an SVAC 有权
    可扩展虚拟设备云（SVAC）和可在SVAC中使用的设备

    公开(公告)号：US08789164B2

    公开(公告)日：2014-07-22

    申请号：US13423107

    申请日：2012-03-16

    申请人： Keshav G. Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    发明人： Keshav G. Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    IPC分类号： G06F21/00

    CPC分类号： H04L63/101 ,  G06F9/45558 ,  H04L45/64 ,  H04L47/125

    摘要： According to one embodiment, a system includes a scalable virtual appliance cloud (SVAC) comprising: at least one distributed line card (DLC); at least one switch fabric coupler (SFC) in communication with the at least one DLC; and at least one controller in communication with the at least one DLC, wherein one or more of the at least one DLC is an appliance DLC, wherein one or more of the at least one SFC is a central SFC, and wherein the SVAC appears to a device external of the SVAC as a single appliance device applying various services to a traffic flow.

    摘要翻译： 根据一个实施例，系统包括可伸缩虚拟设备云（SVAC），其包括：至少一个分布式线路卡（DLC）; 至少一个与所述至少一个DLC通信的交换结构耦合器（SFC）; 以及与所述至少一个DLC通信的至少一个控制器，其中所述至少一个DLC中的一个或多个是设备DLC，其中所述至少一个SFC中的一个或多个是中央SFC，并且其中所述SVAC看起来 作为将各种服务应用于业务流的单个设备设备的SVAC外部的设备。

    Data traffic handling in a distributed fabric protocol (DFP) switching network architecture
    72.
    发明授权
    Data traffic handling in a distributed fabric protocol (DFP) switching network architecture 有权
    分布式架构协议（DFP）交换网络架构中的数据流量处理

    公开(公告)号：US08767722B2

    公开(公告)日：2014-07-01

    申请号：US13594993

    申请日：2012-08-27

    申请人： Keshav Kamble ,  Amitabha Biswas ,  Dar-Ren Leu ,  Chandarani J. Mendon ,  Nilanjan Mukherjee ,  Vijoy Pandey

    发明人： Keshav Kamble ,  Amitabha Biswas ,  Dar-Ren Leu ,  Chandarani J. Mendon ,  Nilanjan Mukherjee ,  Vijoy Pandey

    IPC分类号： H04L12/50 ,  H04Q11/00

    CPC分类号： H04L49/70 ,  H04L47/20 ,  H04L47/627 ,  H04L49/356

    摘要： A switching network includes an upper tier having a master switch and a lower tier including a plurality of lower tier entities. The master switch, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs with which the data traffic is communicated. The master switch applies data handling to the data traffic in accordance with a control policy based at least upon the virtual port in which the data traffic is queued, such that the master switch applies different policies to data traffic queued to two virtual ports on the same port of the master switch.

    摘要翻译： 交换网络包括具有主交换机的上层和包括多个下层实体的较低层。 主交换机具有多个端口，每个端口各自耦合到相应的下层实体，在每个端口上实现多个虚拟端口，每个虚拟端口对应于下层的多个远程物理接口（RPI）中的相应一个 实体耦合到该端口。 在主交换机和RPI之间通信的数据业务在对应于数据业务与之通信的RPI的虚拟端口内排队。 主交换机至少基于数据流量排队的虚拟端口，根据控制策略对数据流量应用数据处理，使得主交换机将不同的策略应用于排队到同一个虚拟端口的数据业务 主交换机的端口

    DIAGNOSTICS IN A DISTRIBUTED FABRIC SYSTEM
    74.
    发明申请
    DIAGNOSTICS IN A DISTRIBUTED FABRIC SYSTEM 有权
    分布式织物系统中的诊断

    公开(公告)号：US20130235735A1

    公开(公告)日：2013-09-12

    申请号：US13414684

    申请日：2012-03-07

    申请人： Sushma Anantharam ,  Nirapada Ghosh ,  Keshav Govind Kamble ,  Dar-Ren Leu ,  Chandarani J. Mendon ,  Nilanjan Mukherjee ,  Vijoy Pandey ,  Nandakumar Peethambaram

    发明人： Sushma Anantharam ,  Nirapada Ghosh ,  Keshav Govind Kamble ,  Dar-Ren Leu ,  Chandarani J. Mendon ,  Nilanjan Mukherjee ,  Vijoy Pandey ,  Nandakumar Peethambaram

    IPC分类号： H04L12/28 ,  H04L12/26

    CPC分类号： H04L49/356 ,  H04L41/12 ,  H04L41/22 ,  H04L43/045 ,  H04L43/0811 ,  H04L43/0817 ,  H04L49/555

    摘要： A distributed fabric system has distributed line card (DLC) chassis and scaled-out fabric coupler (SFC) chassis. Each DLC chassis includes a network processor and fabric ports. Each network processor of each DLC chassis includes a fabric interface in communication with the DLC fabric ports of that DLC chassis. Each SFC chassis includes a fabric element and fabric ports. A communication link connects each SFC fabric port to one DLC fabric port. Each communication link includes cell-carrying lanes. Each fabric element of each SFC chassis collects per-lane statistics for each SFC fabric port of that SFC chassis. Each SFC chassis includes program code that obtains the per-lane statistics collected by the fabric element chip of that SFC chassis. A network element includes program code that gathers the per-lane statistics collected by each fabric element of each SFC chassis and integrates the statistics into a topology of the entire distributed fabric system.

    摘要翻译： 分布式架构系统具有分布式线卡（DLC）机箱和扩展架构耦合器（SFC）机箱。 每个DLC机箱都包括一个网络处理器和Fabric端口。 每个DLC机箱的每个网络处理器包括与该DLC机箱的DLC结构端口通信的结构接口。 每个SFC机箱都包括一个fabric元素和fabric端口。 通信链路将每个SFC Fabric端口连接到一个DLC fabric端口。 每个通信链路包括蜂窝载波通道。 每个SFC机箱的每个结构元素都会收集该SFC机箱的每个SFC结构端口的每通道统计信息。 每个SFC机箱都包含程序代码，用于获取该SFC机箱的结构单元芯片收集的每通道统计信息。 网元包括收集每个SFC机箱的每个结构元素收集的每通道统计信息的程序代码，并将统计信息整合到整个分布式系统的拓扑中。

    Testing memories using algorithm selection
    75.
    发明授权
    Testing memories using algorithm selection 有权
    使用算法选择测试记忆

    公开(公告)号：US07533309B2

    公开(公告)日：2009-05-12

    申请号：US10861851

    申请日：2004-06-04

    申请人： Nilanjan Mukherjee ,  Joseph C. Rayhawk ,  Amrendra Kumar

    发明人： Nilanjan Mukherjee ,  Joseph C. Rayhawk ,  Amrendra Kumar

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/10 ,  G11C29/14 ,  G11C29/16 ,  G11C29/38 ,  G11C2029/3202

    摘要： A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit is disclosed. In a specific example, a determination is made during running of a BIST whether one or more algorithms are to be run. If any algorithm is not designated for running, the particular algorithm is skipped and the test moves to other algorithms to be run. A BIST controller is configured to perform a group of test algorithms. Certain algorithms from the group may be checked to see if they are to be run or bypassed. A delay or skip state is desirably interposed following the inclusion of a particular algorithm and prior to the start of a next algorithm. A determination is made during the delay or skip state whether the next algorithm is to be run. The user may also have the option of running all of the algorithms if desired for performance of a particular BIST.

    摘要翻译： 公开了一种执行电路的至少一个存储元件的内置自检（BIST）的方法。 在具体示例中，在BIST的运行期间确定是否要运行一个或多个算法。 如果没有指定运算的算法，跳过特定的算法，并且测试移动到要运行的其他算法。 BIST控制器被配置为执行一组测试算法。 可以检查组中的某些算法，以查看它们是要运行还是旁路。 期望在包含特定算法之后并且在下一个算法开始之前插入延迟或跳过状态。 在延迟或跳过状态期间确定是否要运行下一个算法。 如果需要执行特定的BIST，用户还可以选择运行所有算法。

    Reduced-pin-count-testing architectures for applying test patterns
    76.
    发明授权
    Reduced-pin-count-testing architectures for applying test patterns 有权
    用于应用测试模式的减少针数测试架构

    公开(公告)号：US07487419B2

    公开(公告)日：2009-02-03

    申请号：US11305849

    申请日：2005-12-16

    申请人： Nilanjan Mukherjee ,  Jay Jahangiri ,  Ronald Press ,  Wu-Tung Cheng

    发明人： Nilanjan Mukherjee ,  Jay Jahangiri ,  Ronald Press ,  Wu-Tung Cheng

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G01R31/318583

    摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

    摘要翻译： 公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。 方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。 例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。 电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。 在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到对应于用于控制电路的一个或多个内部扫描链的测试控制信号的一个或多个边界扫描单元 测试中测试。 该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

    System, method, and computer program product for smoothing
    78.
    发明授权
    System, method, and computer program product for smoothing 有权
    系统，方法和计算机程序产品进行平滑处理

    公开(公告)号：US09082220B2

    公开(公告)日：2015-07-14

    申请号：US10716386

    申请日：2003-11-18

    申请人： Nilanjan Mukherjee

    发明人： Nilanjan Mukherjee

    IPC分类号： G06K9/40 ,  G06T17/20

    CPC分类号： G06T17/20 ,  G06T17/205

    摘要： A system and method for a hybrid, variational, user-controlled, 3D mesh smoothing for orphaned shell meshes. The smoothing model is based on a variational combination of energy and equi-potential minimization theories. A variety of smoothing techniques for predicting a new location for the node-to-smooth are employed. Each node is moved according to a specific smoothing algorithm so as to keep element included angles, skew and distortion to a minimum. The variational smoother selection logic is based on nodal valency and element connectivity pattern of the node to smooth. Results show its consistency with both quadrilateral and quad-dominant meshes with a significant gain over conventional Laplacian schemes in terms of mesh quality, stability, user control and flexibility.

    摘要翻译： 用于孤立壳网格的混合，变体，用户控制的3D网格平滑的系统和方法。 平滑模型基于能量和等效电位最小化理论的变分组合。 采用各种用于预测节点到光滑的新位置的平滑技术。 每个节点根据特定的平滑算法移动，以将元素的夹角，偏斜和失真保持在最小。 变分平滑器选择逻辑基于节点的节点价值和元素连通性模式来平滑。 在网格质量，稳定性，用户控制和灵活性方面，结果表明其与四边形和四重主要网格的一致性在传统拉普拉斯算法方面具有显着的增益。