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公开(公告)号：US20120030537A1
公开(公告)日：2012-02-02
申请号：US13175372
申请日：2011-07-01
摘要： The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.
摘要翻译： 本发明提供了一种通过将符号表征为DATA或NON_DATA中的一种来产生符号表征位，将符号表征位放置在符号的两端并且用符号表征位发送符号来保护符号类型的方法 在两端。 因此，单字节错误可能会影响两个连续符号中的类型位，并将影响单个符号中的一个或另一个类型位，但不能影响单个符号中的两个类型位。
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公开(公告)号：US08047880B2
公开(公告)日：2011-11-01
申请号：US12910722
申请日：2010-10-22
申请人： Stewart Shannon Fields , Matthew K. Herndon , Min Chul Kim , Ron Larson , Richard J. Middlehurst , Anilkumar R. Pannikkat , Glenn Wheelock , Colin Whitby-Strevens
发明人： Stewart Shannon Fields , Matthew K. Herndon , Min Chul Kim , Ron Larson , Richard J. Middlehurst , Anilkumar R. Pannikkat , Glenn Wheelock , Colin Whitby-Strevens
IPC分类号： H01R13/64
CPC分类号： H01R13/506 , H01R13/64
摘要： Connectors having a smaller profile. These connectors are useful as a reduced form factor DisplayPort connector. Keys on a receptacle are used to indicate when an insert is fully engaged. Edges of the receptacle and insert are chamfered in such a way as to prevent the pins of the connector from being damaged when an improper insertion is attempted. User experience is also enhanced by the use of one or more latches. As the connector is inserted, the latch provides resistance that builds until the connector is inserted a certain distance, after which the latch enters a cutout portion of the insert thus releasing the pressure and letting the user know the connection has been made. Fingers are employed to provide mechanical stability and electrical connection between receptacle and insert.
摘要翻译： 具有较小外形的连接器。 这些连接器可用作缩小尺寸的DisplayPort连接器。 插座上的键用于指示插入件何时完全接合。 插座和插入件的边缘被倒角，以防止尝试不当插入时连接器的销钉被损坏。 通过使用一个或多个锁存器也可以增强用户体验。 当连接器被插入时，闩锁提供电阻，直到连接器插入一定距离，之后闩锁进入插入件的切口部分，从而释放压力并让用户知道连接已经进行。 手指用于提供插座和插入件之间的机械稳定性和电连接。
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公开(公告)号：US20100325516A1
公开(公告)日：2010-12-23
申请号：US12869600
申请日：2010-08-26
摘要： The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.
摘要翻译： 本发明提供了一种通过将符号表征为DATA或NON_DATA中的一种来产生符号表征位，将符号表征位放置在符号的两端并且用符号表征位发送符号来保护符号类型的方法 在两端。 因此，单字节错误可能会影响两个连续符号中的类型位，并将影响单个符号中的一个或另一个类型位，但不能影响单个符号中的两个类型位。
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74.发明申请METHODS AND APPARATUS FOR ENSURING COMPATIBILITY ON A HIGH PERFORMANCE SERIAL BUS 有权用于确保高性能串行总线兼容性的方法和装置公开(公告)号：US20100202314A1
公开(公告)日：2010-08-12
申请号：US12763093
申请日：2010-04-19
IPC分类号： H04L12/26
CPC分类号： H04L12/6418 , H04L1/0002 , H04L12/40052 , H04L12/40071
摘要： A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when the BOSS node is idle, determining whether the last packet transmitted by any border node was an Alpha format packet if the BOSS node is idle, and unlocking the Legacy cloud if the last packet transmitted by the border node was not an Alpha format packet.
摘要翻译： 公开了一种数据通信系统，其具有耦合到至少一个Beta云的至少一个Legacy云。 该系统还具有至少一个BOSS节点和至少一个边界节点。 公开了一种用于确保兼容性的方法，包括确定BOSS节点何时空闲，如果BOSS节点空闲，则确定由任何边界节点发送的最后一个分组是否是Alpha格式分组，如果由 边界节点不是Alpha格式数据包。
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75.发明授权Method and apparatus for automatic detection and healing of signal pair crossover on a high performance serial bus 有权用于在高性能串行总线上自动检测和修复信号对交叉的方法和装置公开(公告)号：US07401173B1
公开(公告)日：2008-07-15
申请号：US11139815
申请日：2005-05-27
IPC分类号： G06F13/14
CPC分类号： G06F13/4068 , G06F13/4295
摘要： An automatic crossover and healing process is disclosed for the P1394b standard. In particular, a crossover process is disclosed which comprises coupling the transmitting logic of a PHY to TPA, and coupling the receive logic of a PHY to TPB.
摘要翻译： P1394b标准公开了一种自动交叉和愈合过程。 特别地，公开了一种交叉过程，其包括将PHY的发送逻辑耦合到TPA，以及将PHY的接收逻辑耦合到TPB。
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公开(公告)号：US07389371B2
公开(公告)日：2008-06-17
申请号：US11725711
申请日：2007-03-19
CPC分类号： H04L12/6418 , G06F13/426 , H04L12/40078 , H04L12/40117 , H04L12/40123 , H04L43/50
摘要： A method and apparatus is disclosed for preventing loops in a full-duplex bus The method has the acts of: selecting at least two candidates to join said bus; establishing a dominant candidate from one of the candidates; testing for loops in said bus; and joining said dominant candidate is no loop is found in said bus. Alternate embodiments are shown that utilize unique identifiers to facilitate candidate selection and to establish dominance on the bus.
摘要翻译： 公开了一种用于防止全双工总线中的环路的方法和装置。该方法具有以下动作：选择至少两个候选来加入所述总线; 从候选人之一建立主要候选人; 测试所述总线中的回路; 并加入所述优势候选人是否在所述巴士中找不到循环。 示出了替代实施例，其利用唯一标识符来促进候选者选择并在总线上建立优势。
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公开(公告)号：US07352708B1
公开(公告)日：2008-04-01
申请号：US10635593
申请日：2003-08-05
CPC分类号： H04L12/40052 , H04L12/6418
摘要： A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed.A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border node is disclosed, as is a method for identifying a senior border node Various methods for properly issuing gap tokens within a beta cloud are disclosed.A method for returning control to the senior border node is disclosed. A method for determining whether a BOSS node may issue a grant is disclosed.
摘要翻译： 公开了一种与高性能串行总线系统内的边界节点的行为有关的方法和装置。 公开了一种用于确定和传达混合总线的存在的方法。 公开了一种用于确定到高级边界节点的路径的方法，以及用于识别高级边界节点的方法。公开了用于在beta云内正确发出间隙令牌的各种方法。 公开了一种将控制权返回给高级边界节点的方法。 公开了一种用于确定BOSS节点是否可以发放授权的方法。
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公开(公告)号：US20070257923A1
公开(公告)日：2007-11-08
申请号：US11724994
申请日：2007-03-15
CPC分类号： H04L69/18 , G09G5/006 , G09G2330/06 , G09G2370/10
摘要： Methods and apparatus for harmonizing or unifying at least partly heterogeneous device profiles within electronic devices. In one embodiment, processing or protocol layers within two or more separate device profiles (such as for example the Embedded and External profiles of the UDI specification) are harmonized, thereby permitting the use of a single logical paradigm (for at least one component or process) in place of two or more heterogeneous paradigms under the prior art. In the exemplary context of the aforementioned UDI specification, only a single implementation of the link layer framing logic of a source device, and the frame parsing logic of the sink is needed. Similarly, only one set of compliance tests for this unified paradigm need be developed and implemented.
摘要翻译： 用于在电子设备内协调或统一至少部分异构的设备简档的方法和装置。 在一个实施例中，在两个或多个分离的设备配置文件（例如UDI规范的嵌入式和外部配置文件）内的处理或协议层被协调，从而允许使用单个逻辑范例（对于至少一个组件或过程 ）代替现有技术中的两个或更多个异质范例。 在上述UDI规范的示例性上下文中，仅需要源设备的链路层成帧逻辑的单个实现以及接收器的帧解析逻辑。 同样，需要制定和实施这一统一范式的一套合规性测试。
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公开(公告)号：US20070255871A1
公开(公告)日：2007-11-01
申请号：US11725711
申请日：2007-03-19
IPC分类号： G06F13/00
CPC分类号： H04L12/6418 , G06F13/426 , H04L12/40078 , H04L12/40117 , H04L12/40123 , H04L43/50
摘要： A method and apparatus is disclosed for preventing loops in a full-duplex bus. One method has the acts of: selecting at least two candidates to join said bus; establishing a dominant candidate from one of said at least two candidates; testing for loops in said bus; and joining said dominant candidate if no loops are found in said bus. Another method has the acts of: selecting a plurality candidates to join said bus; establishing at least one dominant candidate; testing for loops in said bus; and joining said at least one dominant candidate if no loops are found in said bus. Alternative embodiments are shown that utilize unique identifiers to facilitate candidate selection and to establish dominance on the bus.
摘要翻译： 公开了一种用于防止全双工总线中的环路的方法和装置。 一种方法有：选择至少两个候选人加入所述总线; 从所述至少两个候选人之一建立主要候选人; 测试所述总线中的回路; 并且如果在所述总线中没有发现循环，则加入所述主要候选者。 另一方法具有以下动作：选择多个候选以加入所述总线; 建立至少一个优势候选人; 测试所述总线中的回路; 以及如果在所述总线中没有发现循环，则加入所述至少一个主要候选者。 示出了替代实施例，其利用唯一标识符来促进候选者选择并在总线上建立优势。
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公开(公告)号：US07194564B2
公开(公告)日：2007-03-20
申请号：US11021337
申请日：2004-12-21
CPC分类号： H04L12/6418 , G06F13/426 , H04L12/40078 , H04L12/40117 , H04L12/40123 , H04L43/50
摘要： A method and apparatus is disclosed for preventing loops in a full-duplex bus. One method has the acts of: selecting at least two candidates to join said bus; establishing a dominant candidate from one of said at least two candidates; testing for loops in said bus; and joining said dominant candidate if no loops are found in said bus.Another method has the acts of: selecting a plurality candidates to join said bus; establishing at least one dominant candidate; testing for loops in said bus; and joining said at least one dominant candidate if no loops are found in said bus. Alternative embodiments are shown that utilize unique identifiers to facilitate candidate selection and to establish dominance on the bus.
摘要翻译： 公开了一种用于防止全双工总线中的环路的方法和装置。 一种方法有：选择至少两个候选人加入所述总线; 从所述至少两个候选人之一建立主要候选人; 测试所述总线中的回路; 并且如果在所述总线中没有发现循环，则加入所述主要候选者。 另一方法具有以下动作：选择多个候选以加入所述总线; 建立至少一个优势候选人; 测试所述总线中的回路; 以及如果在所述总线中没有发现循环，则加入所述至少一个主要候选者。 示出了替代实施例，其利用唯一标识符来促进候选者选择并在总线上建立优势。
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