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    Variation compensation circuitry for memory interface
    73.
    发明授权
    Variation compensation circuitry for memory interface 有权
    用于存储器接口的变差补偿电路

    公开(公告)号：US08565034B1

    公开(公告)日：2013-10-22

    申请号：US13249954

    申请日：2011-09-30

    申请人： Sean Shau-Tu Lu ,  Joseph Huang ,  Yan Chong ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Sean Shau-Tu Lu ,  Joseph Huang ,  Yan Chong ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： G11C7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G06F13/1689

    摘要： Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data and data strobe signals from system memory during read operations. The memory interface circuitry may include de-skew circuitry and dynamic variation compensation circuitry. The de-skew circuitry may be configured during calibration procedures to reduce skew between the data and data strobe signals. The dynamic variation compensation circuitry may be used in real time to compensate for variations in operating conditions. The dynamic variation compensation circuitry may include a phase generation circuit operable to generate data strobe signals having different phases, an edge detection circuit operable to detect leading/trailing edge failures, a control circuit operable to control a counter, and an adjustable delay circuit that is controlled by the counter and that is operable to properly position the data signal with respect to its corresponding data strobe signal.

    摘要翻译： 集成电路可以包括可操作以与系统存储器通信的存储器接口电路。 存储器接口电路可以在读取操作期间从系统存储器接收数据和数据选通信号。 存储器接口电路可以包括去偏移电路和动态变化补偿电路。 可以在校准过程期间配置去偏移电路，以减少数据和数据选通信号之间的偏差。 可以实时地使用动态变化补偿电路来补偿操作条件的变化。 动态变化补偿电路可以包括可产生具有不同相位的数据选通信号的相位产生电路，可操作以检测前沿/后沿故障的边缘检测电路，可操作以控制计数器的控制电路和可调延迟电路， 由计数器控制，并且可操作以相对于其对应的数据选通信号适当地定位数据信号。

    High-performance memory interface circuit architecture
    74.
    发明授权
    High-performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US08305121B1

    公开(公告)日：2012-11-06

    申请号：US13168499

    申请日：2011-06-24

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
    75.
    发明申请
    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES 有权
    可编程逻辑器件中的写层次实现

    公开(公告)号：US20120106264A1

    公开(公告)日：2012-05-03

    申请号：US13349228

    申请日：2012-01-12

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    IPC分类号： G11C7/10 ,  H03L7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

    METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS
    76.
    发明申请
    METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS 有权
    用于最小化信号之间的空白的方法和装置

    公开(公告)号：US20110221497A1

    公开(公告)日：2011-09-15

    申请号：US13019277

    申请日：2011-02-01

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    IPC分类号： H03L7/00 ,  H03H11/26

    CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

    摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

    摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

    High-performance memory interface circuit architecture
    77.
    发明授权
    High-performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US07969215B1

    公开(公告)日：2011-06-28

    申请号：US12467681

    申请日：2009-05-18

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

    Techniques for Providing Reduced Duty Cycle Distortion
    78.
    发明申请
    Techniques for Providing Reduced Duty Cycle Distortion 有权
    提供减少占空比失真的技术

    公开(公告)号：US20110074477A1

    公开(公告)日：2011-03-31

    申请号：US12642502

    申请日：2009-12-18

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的一个延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。 每个可变延迟块和固定延迟块都是反相的。

    READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
    79.
    发明申请
    READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA 有权
    DDR3应用于FPGA的阅读实施

    公开(公告)号：US20080291758A1

    公开(公告)日：2008-11-27

    申请号：US11935310

    申请日：2007-11-05

    申请人： Michael H.M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

    发明人： Michael H.M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

    摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

    摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。