公开(公告)号：US07639032B2

公开(公告)日：2009-12-29

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20080174334A1

公开(公告)日：2008-07-24

申请号：US12061104

申请日：2008-04-02

申请人： Kaushik Chanda ,  Hazara S. Rathore ,  Paul S. McLaughlin ,  Robert D. Edwards ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Chih-Chao Yang ,  Conrad A. Barile

发明人： Kaushik Chanda ,  Hazara S. Rathore ,  Paul S. McLaughlin ,  Robert D. Edwards ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Chih-Chao Yang ,  Conrad A. Barile

IPC分类号： G01R31/26 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G01R31/287 ,  G06F2217/10 ,  G06F2217/70 ,  G06F2217/78

摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.

摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个介电击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。

公开(公告)号：US07314786B1

公开(公告)日：2008-01-01

申请号：US11420121

申请日：2006-06-16

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Chen

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Chen

IPC分类号： H01L21/338 ,  H01L21/8234 ,  H01L21/8222

CPC分类号： H01L29/86 ,  H01L23/5228 ,  H01L2924/0002 ,  H04W36/08 ,  H04W88/08 ,  H04W88/18 ,  H01L2924/00

摘要： A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.

摘要翻译： 公开了一种金属电阻器和电阻器材料以及形成金属电阻器的方法。 金属电阻器可以包括从由以下组成的组中输入的输入金属：铜（Cu），其输入硅（Si），氮（N 2/2），碳（C），钽（ Ta），钛（Ti）和钨（W），以及输入硅（Si），氮（N 2/2），碳（C），钽（Ta），钛 （Ti）和钨（W）。 该方法比常规方法复杂得多，允许通过灌注材料的量控制电阻，并且与传统的BEOL方法兼容。

公开(公告)号：US20070259519A1

公开(公告)日：2007-11-08

申请号：US11381194

申请日：2006-05-02

申请人： Chih-Chao Yang ,  Kaushik Chanda

发明人： Chih-Chao Yang ,  Kaushik Chanda

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  C23C14/046 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76846

摘要： An interconnect structure with a thicker barrier material coverage at the sidewalls of a feature as compared to the thickness of said barrier material at the feature bottom as well as a method of fabricating such an interconnect structure are provided. The interconnect structure of the present invention has improved technology extendibility for the semiconductor industry as compared with prior art interconnect structure in which the barrier material is formed by a conventional PVD process, a conventional ionized plasma deposition, CVD or ALD. In accordance with the present invention, an interconnect structure having a barrier material thickness at the feature sidewalls (wt) greater than the barrier material thickness at the feature bottom (ht) is provided. That is, the wt/ht ratio is equal to, or greater than, 100% in the inventive interconnect structure.

摘要翻译： 提供了与特征底部处的所述阻挡材料的厚度相比，在特征侧壁处具有较厚阻挡材料覆盖的互连结构以及制造这种互连结构的方法。 与现有技术的互连结构相比，本发明的互连结构具有改进的技术可扩展性，其中阻挡材料通过常规PVD工艺，常规电离等离子体沉积，CVD或ALD形成。 根据本发明，具有大于特征底部处的阻挡材料厚度的特征侧壁处的阻挡材料厚度（w ）。 也就是说，本发明的互连结构中的比例等于或大于100％。

公开(公告)号：US07202159B2

公开(公告)日：2007-04-10

申请号：US10809317

申请日：2004-03-24

申请人： Ramanath Ganapathiraman ,  Ahila Krishnamoorthy ,  Kaushik Chanda ,  Shyam P. Murarka

发明人： Ramanath Ganapathiraman ,  Ahila Krishnamoorthy ,  Kaushik Chanda ,  Shyam P. Murarka

IPC分类号： H01L21/4763

CPC分类号： H01L21/02126 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

摘要翻译： 本发明提供一种在集成电路中形成扩散阻挡层，扩散阻挡层和集成电路的方法。 形成扩散阻挡层的方法包括以下步骤：1）制备硅衬底; 2）使硅衬底与包含自组装单层亚单位和溶剂的组合物接触; 和3）除去溶剂。 扩散阻挡层包括自组装单层。 集成电路包括硅衬底，扩散阻挡层和沉积在扩散阻挡层上的金属。 集成电路中的扩散阻挡层共价连接到硅衬底并且包括自组装单层。

公开(公告)号：US08420537B2

公开(公告)日：2013-04-16

申请号：US12127878

申请日：2008-05-28

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L21/76877 ,  H01L21/76883

摘要： Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

摘要翻译： 在150℃至400℃的较高退火温度下实现诸如Cu的金属的重结晶和晶粒生长，例如，通过在Cu上形成金属应力锁定层，例如在短至五至六十分钟的短退火时间 在退火和化学机械抛光之前。 应力锁定层通过将原子扩散抑制到自由表面而延伸Cu的弹性区域，导致退火后在室温下拉伸应力接近零。 从而避免了造成可靠性问题的应力消除。 也实现了改善的晶粒尺寸和纹理。 通过化学机械抛光退火后去除应力锁定层，使Cu互连具有低应力和改善的晶粒尺寸和纹理。

公开(公告)号：US20120111825A1

公开(公告)日：2012-05-10

申请号：US13351370

申请日：2012-01-17

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： B05D5/12 ,  B05D3/10

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US20110186963A1

公开(公告)日：2011-08-04

申请号：US13085632

申请日：2011-04-13

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。

公开(公告)号：US20100314764A1

公开(公告)日：2010-12-16

申请号：US12482777

申请日：2009-06-11

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel Edelstein ,  Baozhen Li

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel Edelstein ,  Baozhen Li

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.

摘要翻译： 一种制造结构的结构和方法。 该结构包括：介电层中的沟槽; 导电衬垫，导电芯导体和填充所述衬套和所述芯导体之间的空隙的导电填充材料。

公开(公告)号：US07732924B2

公开(公告)日：2010-06-08

申请号：US11761495

申请日：2007-06-12

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。