公开(公告)号：US20120272202A1

公开(公告)日：2012-10-25

申请号：US13535675

申请日：2012-06-28

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F17/50

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.

摘要翻译： 一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的方法，其包括从多个客户端接收系统需求，从系统需求中识别公共处理结构和技术，以及将公共处理结构和技术分配给 三层计算机处理芯片堆栈计划。 该方法还包括从系统需求中识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。 该方法还包括确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。 制造设备生成并集成了包括公共结构和技术的层，以及主机层，包括不常见的结构和技术，以形成3D计算机处理芯片堆栈。

公开(公告)号：US20110191776A1

公开(公告)日：2011-08-04

申请号：US12698545

申请日：2010-02-02

申请人： Pradip Bose ,  Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Pradip Bose ,  Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F9/46

CPC分类号： G06F9/46

摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.

摘要翻译： 半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。 每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。 集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。 集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。 当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

公开(公告)号：US20100333056A1

公开(公告)日：2010-12-30

申请号：US12493599

申请日：2009-06-29

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.

摘要翻译： 在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。 对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。 如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。 对于每个含设备的层中的所有相邻的功能块对，重复此例程。 随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。 该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

公开(公告)号：US20100287358A1

公开(公告)日：2010-11-11

申请号：US12435631

申请日：2009-05-05

申请人： Philip G. Emma ,  Allan M. Hartstein ,  Keith N. Langston ,  Brian R. Prasky ,  Thomas R. Puzak ,  Charles F. Webb

发明人： Philip G. Emma ,  Allan M. Hartstein ,  Keith N. Langston ,  Brian R. Prasky ,  Thomas R. Puzak ,  Charles F. Webb

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30047 ,  G06F8/4442 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30076 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/6028

摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

摘要翻译： 一种分支预测方法，所述方法包括：接收具有分支错误猜测指令地址的分支错误猜测指令和包括操作码和分支目标地址的数据，确定分支错误猜测指令是否由分支预测机制预测，发送 分支对执行单元的错误猜测指令响应于确定分支错误猜测指令由分支预测机制预测，以及在分支目标地址处的接收和解码指令。

公开(公告)号：US07551453B2

公开(公告)日：2009-06-23

申请号：US11450258

申请日：2006-06-09

申请人： Ferenc M. Bozso ,  Philip G. Emma

发明人： Ferenc M. Bozso ,  Philip G. Emma

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： G02B6/43 ,  G02B6/12004 ,  G02B6/124 ,  G02B6/3885 ,  G02B6/4246 ,  G02B6/4292 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0274 ,  H05K1/14 ,  H05K2201/044

摘要： An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

公开(公告)号：US20090144492A1

公开(公告)日：2009-06-04

申请号：US12126499

申请日：2008-05-23

申请人： John E. Barth ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth ,  Philip G. Emma ,  Erik L. Hedberg ,  Hillery C. Hunter ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G06F2212/304 ,  Y02D10/13

摘要： A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

摘要翻译： 体现在机器可读数据存储介质上的硬件描述语言（HDL）设计结构包括当在计算机辅助设计系统中处理时生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示的元件。 HDL设计结构还包括划分为可刷新部分和不可刷新部分的DRAM高速缓存; 以及高速缓存控制器，被配置为基于所述高速缓存行的使用历史将输入的各个高速缓存行分配给所述高速缓存的可刷新部分和不可刷新部分之一; 其中对应于具有低于定义频率的使用历史的数据的高速缓存行被控制器分配给高速缓存的可刷新部分，并且与具有等于或高于定义频率的使用历史的数据相对应的高速缓存行被分配给不可刷新 部分缓存。

公开(公告)号：US07526610B1

公开(公告)日：2009-04-28

申请号：US12052160

申请日：2008-03-20

申请人： Philip G. Emma ,  Robert K. Montoye ,  Vijayalakshmi Srinivasan

发明人： Philip G. Emma ,  Robert K. Montoye ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/00

CPC分类号： G06F12/0895 ,  G06F12/0864

摘要： A memory cache comprising, a data sector having a sector ID, wherein the data sector stores a data entry, a primary directory having a primary directory entry, wherein a position of the primary directory entry is defined by a congruence class value and a way value, and a secondary directory corresponding to the data sector having a secondary directory entry corresponding to the data sector, wherein the secondary directory entry include, a primary ID field corresponding to the way value, and a sector ID field operative to identify the sector ID.

摘要翻译： 一种存储器缓存器，包括具有扇区ID的数据扇区，其中所述数据扇区存储数据条目，具有主目录条目的主目录，其中所述主目录条目的位置由所述一致类值和方式值 以及对应于具有与数据扇区相对应的次目录条目的数据扇区的次级目录，其中次目录条目包括对应于方式值的主ID字段和可操作以识别扇区ID的扇区ID字段。

公开(公告)号：US07339963B2

公开(公告)日：2008-03-04

申请号：US10305516

申请日：2002-11-27

申请人： Ferenc M. Bozso ,  Philip G. Emma

发明人： Ferenc M. Bozso ,  Philip G. Emma

IPC分类号： H01S3/00

CPC分类号： H01S5/0428 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/12032 ,  H01L2924/15192 ,  H01S5/02248 ,  H01S5/06226 ,  H01S5/183 ,  H01L2924/00014 ,  H01L2924/00

摘要： A high speed optical channel including an optical driver and a photodetector in a CMOS photoreceiver. The optical channel driver includes a FET driver circuit driving a passive element (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser (VCSEL) diode. The VCSEL diode is biased by a bias supply. The integrated loop inductor may be integrated in CMOS technology and on the same IC chip as either/both of the FET driver and the VCSEL diode. The photodetector is in a semiconductor (silicon) layer that may be on an insulator layer, i.e., SOI. One or more ultrathin metal electrodes (

摘要翻译： 一种包括CMOS光接收器中的光驱动器和光电检测器的高速光通道。 光通道驱动器包括驱动无源元件（例如，集成环路电感器）和垂直腔表面发射激光器（VCSEL）二极管的FET驱动器电路。 VCSEL二极管由偏置电源偏置。 集成环路电感可以集成在CMOS技术中，并且与FET驱动器和VCSEL二极管中的一个或两者集成在同一个IC芯片上。 光电检测器处于半导体（硅）层中，其可以在绝缘体层上，即SOI上。 在硅层上的一个或多个超薄金属电极（<A）形成肖特基势垒二极管结，其又形成了在超薄金属电极和肖特基势垒二极管结之间含有二维电子气的量子阱。

公开(公告)号：US20070290315A1

公开(公告)日：2007-12-20

申请号：US11538567

申请日：2006-10-04

申请人： Philip G. Emma ,  John U. Knickerbocker ,  Cirag S. Patel

发明人： Philip G. Emma ,  John U. Knickerbocker ,  Cirag S. Patel

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

摘要翻译： 计算机芯片被构造成具有至少一个单层芯片，至少一个多层芯片堆叠和以小于100微米直径的电互连为特征的载体封装，其中单层芯片和多层芯片 芯片堆叠都电耦合到载体封装的电互连，并且单层芯片通过载体封装通信地耦合到多层芯片堆叠，使得电信号在单层之间传递给定距离 芯片和多层芯片堆栈，在给定距离内的单层芯片基本上是传播速度。 单层芯片可以是具有多核的处理器，并且多层芯片堆栈可以是存储器高速缓存堆栈。 具有至少高达2500个互连/ cm 2的密度的互连通孔将单层芯片和多层芯片堆叠电耦合到载体封装。

公开(公告)号：US07120327B2

公开(公告)日：2006-10-10

申请号：US10305853

申请日：2002-11-27

申请人： Ferenc M. Bozso ,  Philip G. Emma

发明人： Ferenc M. Bozso ,  Philip G. Emma

IPC分类号： G02B6/26

CPC分类号： G06F13/409 ,  G02B6/43

摘要： An electronic system with components communicating over optical channels, a board initialization and continuity check and a method of transferring data over the optical channels. The system include a backplane with board to board signal wiring and a shared optical bus. Optical gratings are attached to the backplane and to circuit boards to pass optical energy between an optical transceiver and board/backplane. An optical transceiver at each end of each optical jumper relays optical signals between the optical jumpers and the connected circuit board or the backplane. Optical jumpers optically connect the circuit boards to the backplane.

摘要翻译： 具有通过光信道通信的组件的电子系统，板初始化和连续性检查以及通​​过光信道传送数据的方法。 该系统包括具有板对板信号布线和共享光学总线的背板。 光栅连接到背板和电路板以在光收发器和板/背板之间传递光能。 每个光学跳线的每端的光收发器在光学跳线和连接的电路板或背板之间中继光信号。 光跳线将电路板光学连接到背板。