公开(公告)号：US20060284157A1

公开(公告)日：2006-12-21

申请号：US11155202

申请日：2005-06-17

申请人： Shih-Hung Chen ,  Hsiang Lung

发明人： Shih-Hung Chen ,  Hsiang Lung

IPC分类号： H01L29/02

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

公开(公告)号：US09240405B2

公开(公告)日：2016-01-19

申请号：US13089652

申请日：2011-04-19

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC分类号： H01L27/118 ,  H01L27/06 ,  H01L27/02 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/0688 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

摘要翻译： 描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。 用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。 存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。 存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。 这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。 然后可以将单独的电路堆叠并结合在一起。

公开(公告)号：US09224611B2

公开(公告)日：2015-12-29

申请号：US13570411

申请日：2012-08-09

申请人： Shih-Hung Chen ,  Hang-Ting Lue

发明人： Shih-Hung Chen ,  Hang-Ting Lue

IPC分类号： H03K3/00 ,  H01L21/28 ,  H01L23/48 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L21/28282 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/0001

摘要： A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer.

摘要翻译： 提供了一种半导体结构及其制造方法及其操作方法。 半导体结构包括基板，主体结构，第一介电层，第一导电条，第二导电条，第二介电层和导电结构。 主体结构形成在基板上，第一电介质层形成在基板上并围绕主体结构的两个侧壁和顶部。 第一导电条和第二导电条分别形成在第一介电层的两个侧壁上。 第二电介质层形成在第一电介质层，第一导电条和第二导电条上。 导电结构形成在第二电介质层上。

公开(公告)号：US08860202B2

公开(公告)日：2014-10-14

申请号：US13597669

申请日：2012-08-29

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L23/02

CPC分类号： H01L23/36 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip.

摘要翻译： 提供了芯片堆叠结构及其制造方法。 芯片堆叠结构包括第一芯片，第二芯片和垂直导线。 第二芯片设置在第一芯片上方。 垂直导线与第一芯片和第二芯片电连接。 垂直导线设置在第一芯片和第二芯片的投影区域的外侧。

公开(公告)号：US20140197516A1

公开(公告)日：2014-07-17

申请号：US13739914

申请日：2013-01-11

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC分类号： H01L21/66 ,  H01L29/06

CPC分类号： H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

摘要翻译： 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20140061947A1

公开(公告)日：2014-03-06

申请号：US13597669

申请日：2012-08-29

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/36 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip.

摘要翻译： 提供了芯片堆叠结构及其制造方法。 芯片堆叠结构包括第一芯片，第二芯片和垂直导线。 第二芯片设置在第一芯片上方。 垂直导线与第一芯片和第二芯片电连接。 垂直导线设置在第一芯片和第二芯片的投影区域的外侧。

公开(公告)号：US20140043067A1

公开(公告)日：2014-02-13

申请号：US13570411

申请日：2012-08-09

申请人： Shih-Hung Chen ,  Hang-Ting Lue

发明人： Shih-Hung Chen ,  Hang-Ting Lue

IPC分类号： H03K3/00 ,  H01L21/28 ,  H01L23/48

CPC分类号： H01L21/28282 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/0001

摘要： A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer.

摘要翻译： 提供了一种半导体结构及其制造方法及其操作方法。 半导体结构包括基板，主体结构，第一介电层，第一导电条，第二导电条，第二介电层和导电结构。 主体结构形成在基板上，第一电介质层形成在基板上并围绕主体结构的两个侧壁和顶部。 第一导电条和第二导电条分别形成在第一介电层的两个侧壁上。 第二电介质层形成在第一电介质层，第一导电条和第二导电条上。 导电结构形成在第二电介质层上。

公开(公告)号：US08644077B2

公开(公告)日：2014-02-04

申请号：US13707632

申请日：2012-12-07

申请人： Hang-Ting Lue ,  Shih-Hung Chen

发明人： Hang-Ting Lue ,  Shih-Hung Chen

IPC分类号： G11C16/00

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a s tring selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

摘要翻译： 提供了一种存储器件，其制造方法和操作方法。 存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。 堆叠结构设置在基板上。 堆叠结构中的每一个包括一个选择线，字线，地选择线和绝缘线。 串选择线，字线和接地选择线通过绝缘线彼此分离。 通道元件设置在堆叠结构之间。 电介质元件设置在通道元件和堆叠结构之间。 源元件设置在基板的上表面和通道元件的下表面之间。 位线设置在通道元件的上表面上。

公开(公告)号：US08492216B2

公开(公告)日：2013-07-23

申请号：US13014048

申请日：2011-01-26

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/417 ,  H01L21/743 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/1022 ,  H01L29/41708

摘要： The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.

摘要翻译： 本发明涉及一种半导体结构及其制造方法。 半导体结构包括半导体衬底，隔离层，第一金属层和第二金属层。 半导体衬底包括上衬底表面和在上衬底表面下方的半导体器件。 隔离层与第一侧壁和第二侧壁相对。 第一金属层设置在上基板表面上。 第一金属层和第二金属层分别设置在第一侧壁和第二侧壁上。 第二金属层的下表面在上基板表面下方。

公开(公告)号：US20130119457A1

公开(公告)日：2013-05-16

申请号：US13707632

申请日：2012-12-07

申请人： Hang-Ting Lue ,  Shih-Hung Chen

发明人： Hang-Ting Lue ,  Shih-Hung Chen

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

摘要翻译： 提供了一种存储器件，其制造方法和操作方法。 存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。 堆叠结构设置在基板上。 每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。 串选择线，字线和接地选择线通过绝缘线彼此分离。 通道元件设置在堆叠结构之间。 电介质元件设置在通道元件和堆叠结构之间。 源元件设置在基板的上表面和通道元件的下表面之间。 位线设置在通道元件的上表面上。