CHECKPOINTING IN MASSIVELY PARALLEL PROCESSING
    71.
    发明申请
    CHECKPOINTING IN MASSIVELY PARALLEL PROCESSING 有权
    检查在大规模并行处理

    公开(公告)号:US20110119525A1

    公开(公告)日:2011-05-19

    申请号:US12618675

    申请日:2009-11-13

    IPC分类号: G06F11/07 G06F15/16

    CPC分类号: G06F11/1438

    摘要: One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory.

    摘要翻译: 一个实施例是在大量并行处理(MPP)系统中的处理节点处执行本地检查点的方法,其执行与多个处理节点的工作负载。 本地检查点存储在处理节点的本地存储器中。 当工作负载继续执行时,从本地存储器中存储的本地检查点执行全局检查点。

    Telepresence system with automatic preservation of user head size
    72.
    发明授权
    Telepresence system with automatic preservation of user head size 失效
    网真系统具有自动保存用户头大小

    公开(公告)号:US07388981B2

    公开(公告)日:2008-06-17

    申请号:US10376435

    申请日:2003-02-27

    IPC分类号: G06K9/00

    摘要: A method and system for mutually immersive telepresencing are provided. A user is viewed at a user's location to provide a user's image. The size of the user's head is determined in the user's image. A surrogate having a surrogate's face display about the size of the user's head is provided. The user's image is processed based on the size of the surrogate's face display to provide an about life-size image of the user's head. The about life-size image is displayed on the surrogate's face display.

    摘要翻译: 提供了一种相互沉浸式远程休假的方法和系统。 在用户的位置查看用户以提供用户的图像。 在用户的图像中确定用户头部的大小。 提供了具有代表人脸的代理关于用户头部的尺寸的代理。 基于代理人的脸部显示的大小来处理用户的图像,以提供关于用户头部的真实尺寸的图像。 关于生命大小的图像显示在代理人的脸部显示上。

    HIGH PERFORMANCE PERSISTENT MEMORY
    74.
    发明申请
    HIGH PERFORMANCE PERSISTENT MEMORY 审中-公开
    高性能的记忆

    公开(公告)号:US20150261461A1

    公开(公告)日:2015-09-17

    申请号:US14423913

    申请日:2012-08-28

    IPC分类号: G06F3/06 G06F12/08

    摘要: A method of performing data transactions in a high performance persistent memory comprising, with a processor, updating data by writing new data to non-volatile memory (NVM) and receiving a done signal from a transaction accelerator communicatively coupled to the NVM. An apparatus for high performance persistent memory, comprising a processor, a memory controller communicatively coupled to the processor, and non-volatile memory communicatively coupled to the memory controller and processor, the non-volatile memory comprising an ACID transaction accelerator, in which the processor updates data on the non-volatile memory (NVM) by writing new data to the NVM, and receives a done signal from the an ACID transaction accelerator when the data has been updated.

    摘要翻译: 一种在高性能持久存储器中执行数据交易的方法,包括与处理器通过将新数据写入非易失性存储器(NVM)来更新数据,以及从通信地耦合到NVM的事务处理加速器接收完成信号。 一种用于高性能持久存储器的装置,包括处理器,通信地耦合到处理器的存储器控​​制器和通信地耦合到存储器控制器和处理器的非易失性存储器,非易失性存储器包括ACID事务加速器,其中处理器 通过向NVM写入新数据来更新非易失性存储器(NVM)上的数据,并且当更新数据时,从ACID事务加速器接收完成信号。

    METHODS AND APPARATUS TO PERFORM ERROR DETECTION AND CORRECTION
    76.
    发明申请
    METHODS AND APPARATUS TO PERFORM ERROR DETECTION AND CORRECTION 有权
    执行错误检测和校正的方法和设备

    公开(公告)号:US20130111295A1

    公开(公告)日:2013-05-02

    申请号:US13285742

    申请日:2011-10-31

    IPC分类号: H03M13/29 G06F11/10

    CPC分类号: G06F11/1064

    摘要: Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.

    摘要翻译: 公开了用于执行错误检测和校正的示例性方法,装置和制造。 所公开的示例性方法涉及使存储器控制器能够以标记存储器模式或非标记存储器模式之一进行操作。 另外,当在存储器控制器中启用标记存储器模式时,选择五错误校正六错误检测每脉冲串模式以对数据执行纠错。 当在存储器控制器中启用非标记存储器模式时,每个突发模式的六错误校正七错误检测或单错误校正双错误检测每传输模式之一是 根据数据中的错误类型的模式进行选择。

    Altering a degree of redundancy used during execution of an application
    78.
    发明授权
    Altering a degree of redundancy used during execution of an application 有权
    改变在执行应用程序期间使用的一定程度的冗余

    公开(公告)号:US08037350B1

    公开(公告)日:2011-10-11

    申请号:US12250367

    申请日:2008-10-13

    IPC分类号: G06F11/00

    摘要: Processor operating methods and integrated circuits are described. According to one embodiment, a processor operating method includes executing an application using a first number of a plurality of processor cores. The method also includes, during the executing using the first number, evaluating a transition criterion and after the evaluating, executing the application using a second number of the plurality of processor cores. According to another embodiment, an integrated circuit includes a plurality of processor cores and processing circuitry. The processing circuitry is configured to configure a first number of the plurality of processor cores to execute an application, evaluate a transition criterion, and, in response to evaluating the transition criterion, configure a second number of the plurality of processor cores to execute the application. Additional embodiments are described in the disclosure.

    摘要翻译: 描述处理器操作方法和集成电路。 根据一个实施例,处理器操作方法包括使用第一数量的多个处理器核来执行应用。 该方法还包括在使用第一个数字的执行期间评估转换标准,并且在评估之后,使用多个处理器核心的第二数量来执行应用程序。 根据另一个实施例,集成电路包括多个处理器核心和处理电路。 处理电路被配置为配置多个处理器核的第一数量以执行应用,评估转换标准,并且响应于评估转换标准,配置多个处理器核的第二数量以执行应用 。 在本公开中描述了另外的实施例。

    Heterogeneous processor core systems for improved throughput
    79.
    发明授权
    Heterogeneous processor core systems for improved throughput 有权
    异构处理器核心系统,提高吞吐量

    公开(公告)号:US07996839B2

    公开(公告)日:2011-08-09

    申请号:US10621067

    申请日:2003-07-16

    IPC分类号: G06F9/46 G06F15/76 G06F11/30

    CPC分类号: G06F9/5044 G06F9/5088

    摘要: A computer system for maximizing system and individual job throughput includes a number of computer hardware processor cores that differ amongst themselves in at least in their respective resource requirements and processing capabilities. A monitor gathers performance metric information from each of the computer hardware processor cores that are specific to a particular run of application software then executing. Based on these metrics, a workload assignment mechanism assigns jobs to processor cores in order to maximize overall system throughput and the throughput of individual jobs.

    摘要翻译: 用于最大化系统和单个作业吞吐量的计算机系统包括多个计算机硬件处理器核心,其至少在它们各自的资源需求和处理能力中彼此不同。 监视器从特定于特定应用软件运行的每个计算机硬件处理器核心收集性能指标信息,然后执行。 基于这些指标,工作负载分配机制将作业分配给处理器核心,以最大化整体系统吞吐量和单个作业的吞吐量。

    Selective availability in processor systems
    80.
    发明授权
    Selective availability in processor systems 有权
    处理器系统中的选择性可用性

    公开(公告)号:US07941698B1

    公开(公告)日:2011-05-10

    申请号:US12252144

    申请日:2008-10-15

    IPC分类号: G06F11/00

    摘要: Processor operating methods and integrated circuits are described. According to one embodiment, an integrated circuit includes a processor configured to execute a first application and to redundantly execute a second application while executing the first application, the first application being different from the second application. According to another embodiment, a processor operating method includes receiving a request to execute an application using a processor having a plurality of processor cores. The method also includes, in response to the receiving, determining whether the application should be executed redundantly or non-redundantly, non-redundantly executing the application using one processor core of the plurality if the determining comprises determining that the application should be executed non-redundantly, and redundantly executing the application using two or more processor cores of the plurality if the determining comprises determining that the application should be executed redundantly.

    摘要翻译: 描述处理器操作方法和集成电路。 根据一个实施例,集成电路包括被配置为执行第一应用并且在执行第一应用时冗余地执行第二应用的处理器,所述第一应用与第二应用不同。 根据另一个实施例,处理器操作方法包括使用具有多个处理器核的处理器来接收执行应用的请求。 所述方法还包括:响应于所述接收,确定所述应用是否应该被冗余地执行或非冗余地执行,如果所述确定包括确定所述应用应该被执行,则非冗余地执行所述应用的多个处理器核心, 冗余地并冗余地执行应用程序,如果确定包括确定该应用程序应该被冗余执行,则使用多个的两个或多个处理器核心。