公开(公告)号：US20090161738A1

公开(公告)日：2009-06-25

申请号：US12283652

申请日：2008-09-15

申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC分类号： H04L7/00 ,  H04B1/38

CPC分类号： H04L25/14

摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US20080246516A1

公开(公告)日：2008-10-09

申请号：US11696575

申请日：2007-04-04

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

IPC分类号： H03D13/00

CPC分类号： H03D13/004

摘要： A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

摘要翻译： 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。

公开(公告)号：US08816745B1

公开(公告)日：2014-08-26

申请号：US13316361

申请日：2011-12-09

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03L5/00

CPC分类号： H04L25/03878 ,  H03K19/018507

摘要： An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.

摘要翻译： 提供了包括基于电感器和非电感器的均衡器级的均衡器电路。 在一个实现中，均衡器电路包括第一均衡器电路，其包括基于第一电感器的均衡器级和耦合到基于第一电感器的均衡器级的基于非电感器的第一非均衡器级。 在一个实现中，均衡器电路还包括包括多个基于电感器的均衡器级的第二均衡器电路，其中多个基于电感器的均衡器级包括基于第一电感器的均衡器级。 在一个实现中，第一均衡器电路还包括耦合到基于第一电感器的均衡器级和基于非电感器的第一非均衡级的基于第二电感器的均衡器级。

公开(公告)号：US08705605B1

公开(公告)日：2014-04-22

申请号：US13288701

申请日：2011-11-03

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L1/243 ,  H04B17/14 ,  H04L25/03878 ,  H04W52/0274 ,  Y02D70/00

摘要： Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.

摘要翻译： 提供了集成电路（IC）中串行回送测试的设备和方法。 为了实现环回测试，IC的接收机的均衡器级掉电。 此外，均衡器级的共模电压被减小和/或均衡器级的体积节点连接到地。 这样做可以减少来自缓冲器的输入引脚的电容耦合的影响，从而提高环回输出信号的质量。

公开(公告)号：US08416898B1

公开(公告)日：2013-04-09

申请号：US12483151

申请日：2009-06-11

申请人： Mei Luo ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

发明人： Mei Luo ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

IPC分类号： H04B1/10

CPC分类号： H04L25/03057 ,  H04L2025/03592

摘要： A circuit includes a receiver circuit, a decision feedback equalizer circuit, and a control loop circuit. The receiver circuit receives a data signal and generates an input signal in response to the data signal. The decision feedback equalizer circuit includes a tap driver and a first current source coupled to the tap driver. The tap driver drives the input signal based on a tap weight. The control loop circuit varies a current through the first current source based on variations in the input signal to reduce changes in the tap weight that are caused by the variations in the input signal.

摘要翻译： 电路包括接收器电路，判决反馈均衡器电路和控制回路电路。 接收器电路接收数据信号并响应于数据信号产生输入信号。 判决反馈均衡器电路包括抽头驱动器和耦合到抽头驱动器的第一电流源。 抽头驱动器根据抽头重量驱动输入信号。 控制回路电路基于输入信号的变化改变通过第一电流源的电流，以减少由输入信号的变化引起的抽头重量的变化。

公开(公告)号：US08228102B1

公开(公告)日：2012-07-24

申请号：US12717062

申请日：2010-03-03

申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条 侧。 可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。 另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。 每个PMA三元组模块包括第一，第二和第三通道。 第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。 还公开了其它实施例和特征。

公开(公告)号：US08188774B1

公开(公告)日：2012-05-29

申请号：US12833718

申请日：2010-07-09

申请人： Gopi Krishnamurthy ,  Binh Ton ,  Ning Xue ,  Tim Tri Hoang ,  Michael Menghui Zheng ,  Weiqi Ding

发明人： Gopi Krishnamurthy ,  Binh Ton ,  Ning Xue ,  Tim Tri Hoang ,  Michael Menghui Zheng ,  Weiqi Ding

IPC分类号： H03L7/00

CPC分类号： H03K19/1774

摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

摘要翻译： 一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。 收发器通道的偏移校准由物理介质连接电路执行。 传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。 随后，当集成电路的核心部件变得可操作时，该接口被激活。 另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。 另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。 还公开了其它实施例，方面和特征。

公开(公告)号：US08063807B1

公开(公告)日：2011-11-22

申请号：US12433310

申请日：2009-04-30

申请人： Tin H. Lai ,  Sergey Shumarayev ,  Tim Tri Hoang

发明人： Tin H. Lai ,  Sergey Shumarayev ,  Tim Tri Hoang

IPC分类号： H03M1/06

CPC分类号： H04L25/03019 ,  H03G5/165 ,  H04L25/03885

摘要： An equalization circuitry that includes a digital-to-analog converter having a voltage divider and a multiplexer coupled to the voltage divider is described. In one implementation, the digital-to-analog converter provides a control signal to a plurality of single-stage equalizer control logic circuits. Also, in one implementation, the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs. Furthermore, in one implementation, the voltage divider includes a plurality of resistors coupled in series. Also, in one implementation, the voltage divider further includes a first resistor coupled to the plurality of resistors, ground, and a lowest voltage input terminal of the multiplexer, where a voltage across the first resistor is an input voltage to the lowest voltage input terminal. Additionally, in one implementation, the voltage divider further includes a second resistor coupled to the plurality of resistors and a supply voltage, where the supply voltage minus a voltage across the second resistor and a voltage across a resistor of the plurality of resistors is an input voltage to a highest voltage input terminal of the multiplexer. In one implementation, the first and second resistors are programmable in user mode.

摘要翻译： 描述了包括具有分压器和耦合到分压器的多路复用器的数模转换器的均衡电路。 在一个实现中，数模转换器向多个单级均衡器控制逻辑电路提供控制信号。 而且，在一个实现中，多路复用器从分压器接收多个输入并选择多个输入的输出。 此外，在一个实施方式中，分压器包括串联耦合的多个电阻器。 此外，在一个实施方式中，分压器还包括耦合到多个电阻器的接地的第一电阻器和多路复用器的最低电压输入端子，其中第一电阻器两端的电压是输入电压到最低电压输入端子 。 此外，在一个实施方式中，分压器还包括耦合到多个电阻器的第二电阻器和电源电压，其中电源电压减去第二电阻器两端的电压和多个电阻器两端的电阻器两端的电压是输入 电压到多路复用器的最高电压输入端。 在一个实现中，第一和第二电阻器在用户模式下是可编程的。

公开(公告)号：US08049532B1

公开(公告)日：2011-11-01

申请号：US12823596

申请日：2010-06-25

申请人： Simardeep Maangat ,  Vinh Van Ho ,  Tim Tri Hoang

发明人： Simardeep Maangat ,  Vinh Van Ho ,  Tim Tri Hoang

IPC分类号： H03K19/0175 ,  H03L5/00

CPC分类号： H03L7/085 ,  H03K19/017509 ,  H03L7/087

摘要： A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.

摘要翻译： 提出了一种具有连接到输出级的输入端的薄栅极晶体管的电平移动电路。 电平移位电路具有接收处于第一电压的输入的输入级。 具有薄栅极氧化物的晶体管具有连接到输入级的一个端子和耦合到输出级的输入的另一个端子。 电平移位电路的输出级由厚栅极氧化物晶体管实现。

公开(公告)号：US07633349B2

公开(公告)日：2009-12-15

申请号：US11696575

申请日：2007-04-04

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

IPC分类号： H03L1/00

CPC分类号： H03D13/004

摘要： A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

摘要翻译： 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。