公开(公告)号：US20090065834A1

公开(公告)日：2009-03-12

申请号：US11850798

申请日：2007-09-06

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L27/146

CPC分类号： H01L27/14636 ,  H01L27/14625

摘要： A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.

摘要翻译： 一种包括有源像素单元阵列的CMOS图像传感器。 每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。 形成的透光导线结构提供电和光学功能。 通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。 或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。 用于导线层的电气功能包括用作电容器板，电阻器或互连件。

公开(公告)号：US07498208B2

公开(公告)日：2009-03-03

申请号：US11689549

申请日：2007-03-22

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/00

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/42384 ,  H01L29/785

摘要： Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs has a fin with a lower mobility top surface. To inhibit inversion of the top surface, this MOSFET has a gate dielectric layer with a thicker region on the top surface than it does on the opposing sidewall surfaces. Additionally, several techniques for forming the thicker region of the gate dielectric layer are also disclosed.

摘要翻译： 这里公开了在同一衬底上形成有两个不同类型的三栅极MOSFET的结构。 每个MOSFET包括对于特定类型的MOSFET具有最佳移动性的鳍。 由于用于在相同衬底上形成具有不同结晶取向的鳍片的工艺，所以MOSFET中的一个具有具有较低迁移率顶表面的翅片。 为了抑制顶表面的反转，该MOSFET具有栅极电介质层，在顶表面上具有比在相对侧壁表面上更厚的区域。 此外，还公开了用于形成栅极电介质层的较厚区域的几种技术。

公开(公告)号：US20090020806A1

公开(公告)日：2009-01-22

申请号：US11778185

申请日：2007-07-16

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7835

摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

摘要翻译： 公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供 改进的驱动电流，电路延迟最小）。 具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻 值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

公开(公告)号：US20080315264A1

公开(公告)日：2008-12-25

申请号：US11764948

申请日：2007-06-19

申请人： Alberto Escobar ,  Brian J. Greene ,  Edward J. Nowak

发明人： Alberto Escobar ,  Brian J. Greene ,  Edward J. Nowak

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L29/66575 ,  H01L29/7849

摘要： Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

摘要翻译： 公开了具有降低的驱动电流温度灵敏度的场效应晶体管（FET）的实施例。 具体地说，通过与应变相关的载流子迁移率变化相反的FET通道区域中任何温度依赖的载流子迁移率变化被同时抵消，以确保驱动电流响应于温度变化保持近似恒定或至少在预定范围内。 这种相反的应变依赖性载流子迁移率变化由应变结构提供，该应变结构被配置为在通道区域上赋予预选的应变类型的温度相关量。 还公开了形成场效应晶体管的相关方法的实施例。

公开(公告)号：US20080299711A1

公开(公告)日：2008-12-04

申请号：US12175528

申请日：2008-07-18

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/84

摘要： Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

摘要翻译： 公开了具有具有侧壁通道的第一FET和具有平面通道的第二FET的互补CMOS器件。 第一个FET可以是p-FET，第二个FET可以是n-FET，反之亦然。 用于形成不同类型FET的栅电极的导体是不同的，并且是预选的以优化性能。 例如，p-FET栅极材料可以在价带附近具有功函数，并且n-FET栅电极材料可以在导带附近具有功函数。 第一FET的第一栅电极位于与侧壁通道相邻并且第二FET的第二栅电极位于平面通道上方。 然而，器件结构是唯一的，因为第二栅电极横向于第一FET上方延伸并且电耦合到第一栅电极。

公开(公告)号：US20080284021A1

公开(公告)日：2008-11-20

申请号：US11749898

申请日：2007-05-17

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76885 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76867 ,  H01L21/76895 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).

摘要翻译： 一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。 该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。 结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。 在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

公开(公告)号：US07449735B2

公开(公告)日：2008-11-11

申请号：US11548020

申请日：2006-10-10

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/84

摘要： Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

摘要翻译： 公开了具有具有侧壁通道的第一FET和具有平面通道的第二FET的互补CMOS器件。 第一个FET可以是p-FET，第二个FET可以是n-FET，反之亦然。 用于形成不同类型FET的栅电极的导体是不同的，并且是预选的以优化性能。 例如，p-FET栅极材料可以在价带附近具有功函数，并且n-FET栅电极材料可以在导带附近具有功函数。 第一FET的第一栅电极位于与侧壁通道相邻并且第二FET的第二栅电极位于平面通道上方。 然而，器件结构是唯一的，因为第二栅电极横向于第一FET上方延伸并且电耦合到第一栅电极。

公开(公告)号：US20080200021A1

公开(公告)日：2008-08-21

申请号：US12104570

申请日：2008-04-17

申请人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

发明人： Kevin K. Chan ,  Jia Chen ,  Shih-Fen Huang ,  Edward J. Nowak

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

摘要翻译： 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。

公开(公告)号：US20080185649A1

公开(公告)日：2008-08-07

申请号：US12099211

申请日：2008-04-08

申请人： Brent A. Anderson ,  Matthew J. Breitwisch ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Matthew J. Breitwisch ,  Edward J. Nowak

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

摘要翻译： 公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。 具体地说，后门结合在翅片的下部。 三栅结构形成在翅片上并与后门电隔离。 背栅可用于控制FET的阈值电压。 在一个实施例中，背栅极延伸到p型硅衬底中的n阱。 与n阱的接触允许将电压施加到后门。 在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。 在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。 与n型多晶硅层的接触允许电压施加到后门。 通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

公开(公告)号：US20080173953A1

公开(公告)日：2008-07-24

申请号：US11624324

申请日：2007-01-18

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823878 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665

摘要： Structures and related methods including fully silicided regions are disclosed. In one embodiment, a structure includes a substrate; a partially silicided region located in an active region of an integrated circuit formed on the substrate; a fully silicided region located in a non-active region of the integrated circuit, and wherein the partially and fully silicided regions are formed from a common semiconductor layer.

摘要翻译： 公开了包括完全硅化物区域的结构和相关方法。 在一个实施例中，结构包括基底; 位于形成在所述基板上的集成电路的有源区中的部分硅化区; 位于所述集成电路的非有源区中的完全硅化区域，并且其中所述部分和全硅化区域由公共半导体层形成。