公开(公告)号：US5751976A

公开(公告)日：1998-05-12

申请号：US601993

申请日：1996-02-15

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US5317747A

公开(公告)日：1994-05-31

申请号：US666066

申请日：1991-03-07

申请人： Tetsuya Mochida ,  Kouichi Okazawa ,  Kouichi Kimura ,  Hitoshi Kawaguchi ,  Kazushi Kobayashi

发明人： Tetsuya Mochida ,  Kouichi Okazawa ,  Kouichi Kimura ,  Hitoshi Kawaguchi ,  Kazushi Kobayashi

IPC分类号： G06F13/24 ,  G06F9/46 ,  G06F15/16

CPC分类号： G06F13/24

摘要： An interruption control device for controlling interruption requests in a multiprocessor system having a plurality of processor elements and a plurality of peripheral devices. The interruption control device is connected between the processor elements and the peripheral devices. The interruption control device includes a plurality of interruption request registers for indicating the occurrence of an interruption request from either a processor element or a peripheral device to a processor element and a plurality of interruption enable registers for authorizing an interruption request of a processor element. The interruption request registers are read by the processor element being interrupted to identify the source of the interruption request.

摘要翻译： 一种用于控制具有多个处理器元件和多个外围设备的多处理器系统中的中断请求的中断控制装置。 中断控制装置连接在处理器元件和外围设备之间。 中断控制装置包括用于指示从处理器元件或外围设备到处理器元件的中断请求的发生的多个中断请求寄存器以及用于授权处理器元件的中断请求的多个中断使能寄存器。 中断请求寄存器被处理器元件中断，以识别中断请求的源。

公开(公告)号：US5276818A

公开(公告)日：1994-01-04

申请号：US512810

申请日：1990-04-20

申请人： Koichi Okazawa ,  Hiroaki Aotsu ,  Hitoshi Kawaguchi ,  Masami Jikihara ,  Kazushi Kobayashi ,  Koichi Kimura ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Hiroaki Aotsu ,  Hitoshi Kawaguchi ,  Masami Jikihara ,  Kazushi Kobayashi ,  Koichi Kimura ,  Tetsuya Mochida

IPC分类号： G06F13/28 ,  G06F13/36 ,  G06F13/364 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217 ,  G06F13/364

摘要： A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.

摘要翻译： 一种用于信息处理系统的总线系统，其中在公共总线上控制多个模块之间的数据传输。 响应于来自模块的总线使用请求，发出用于中止由具有较低优先级的另一模块执行的数据传输的命令。 正在传送数据的模块通过发出一个指示要传送的字是最终字的信号来响应中止命令。 通过与从总线控制器提供的时钟同步的与数据具有相同宽度的地址总线，在主机和从机之间传送数据。