-
公开(公告)号：US11121716B2
公开(公告)日：2021-09-14
申请号：US17027570
申请日：2020-09-21
发明人： Soyeong Shin , Han-Gon Ko , Deog-Kyoon Jeong
摘要： A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.
-
公开(公告)号：US20210281254A1
公开(公告)日：2021-09-09
申请号：US17193532
申请日：2021-03-05
摘要： A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.
-
公开(公告)号：US20210281253A1
公开(公告)日：2021-09-09
申请号：US16474564
申请日：2017-03-29
申请人： Intel IP Corporation
IPC分类号： H03K5/00
摘要： A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.
-
公开(公告)号：US20210281221A1
公开(公告)日：2021-09-09
申请号：US17190570
申请日：2021-03-03
申请人： NXP USA, Inc.
发明人： Anthony Lamy , Olivier Lembeye
摘要： Embodiments of a device and method are disclosed. In an embodiment, a Doherty amplifier module includes a first amplifier die with a first output terminal, a second amplifier die with a second output terminal, and a wideband impedance inverter circuit electrically coupled between the first and second output terminals. The wideband impedance inverter circuit includes a network of capacitors, the network of capacitors including at least a series capacitor having a positive capacitance, a first shunt circuit having a first negative capacitance, and a second shunt circuit having a second negative capacitance.
-
75.发明授权公开(公告)号：US11115039B2
公开(公告)日：2021-09-07
申请号：US17057702
申请日：2019-05-13
发明人： Ting Li , Zhengbo Huang , Yong Zhang , Yabo Ni , Jian'an Wang , Dongbing Fu
摘要： The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.
-
公开(公告)号：US11108385B1
公开(公告)日：2021-08-31
申请号：US16907948
申请日：2020-06-22
申请人： PixArt Imaging Inc.
发明人： Chung-Min Thor , Kuan-Choong Shim , Gim-Eng Chew
摘要： There is provided a phase shifter circuit of an optical encoder that receives four signals generated from photodiodes. The phase shifter circuit includes four resistor strings each coupled to two of the four signals having a 90-degrees phase pitch. By taping out different numbers of signals at different tape-out nodes of each of the four resistor strings, the phase shifter circuit is adapted to output signals for different interpolation factors without changing the mask set.
-
公开(公告)号：US11061429B2
公开(公告)日：2021-07-13
申请号：US15795214
申请日：2017-10-26
发明人： Greg Sadowski , Shomit N. Das
IPC分类号： G06F1/08 , G01R31/317 , G01R31/28 , H03K5/00 , G11C7/22
摘要： A technique for fine-granularity speed binning for a processing device is provided. The processing device includes a plurality of clock domains, each of which may be clocked with independent clock signals. The clock frequency at which a particular clock domain may operate is determined based on the longest propagation delay between clocked elements in that particular clock domain. The processing device includes measurement circuits for each clock domain that measure such propagation delay. The measurement circuits are replica propagation delay paths of actual circuit elements within each particular clock domain. A speed bin for each clock domain is determined based on the propagation delay measured for the measurement circuits for a particular clock domain. Specifically, a speed bin is chosen that is associated with the fastest clock speed whose clock period is longer than the slowest propagation delay measured for the measurement circuit for the clock domain.
-
公开(公告)号：US20210211314A1
公开(公告)日：2021-07-08
申请号：US16995086
申请日：2020-08-17
发明人： Philjae JEON
摘要： Disclosed is electronic device configured to switch a power mode from a first mode to a second mode as a first time interval and a second time interval sequentially pass. The electronic device includes a first mode receiver, a second mode detector, and a second mode verifier. The first mode receiver outputs a first detection signal, based on three or more receive signals, when the first time interval begins. The second mode detector outputs a second detection signal, based on the first detection signal and a change in voltage levels of the three or more receive signals, when the second time interval begins. When the second detection signal is received, the second mode verifier detects an option pattern generated by the three or more receive signals and verifies that the second time interval begins.
-
公开(公告)号：US20210211132A1
公开(公告)日：2021-07-08
申请号：US17078708
申请日：2020-10-23
摘要： An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.
-
公开(公告)号：US20210175855A1
公开(公告)日：2021-06-10
申请号：US16705868
申请日：2019-12-06
发明人： Rangakrishnan Srinivasan , Mustafa H. Koroglu , Zhongda Wang , Francesco Barale , Abdulkerim L. Coban , John M. Khoury , Sriharsha Vasadi , Michael S. Johnson , Vitor Pereira
摘要： A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.
-
-
-
-
-
-
-
-
-
搜索结果
4650 条记录 (耗时 0.039 秒)