公开(公告)号：US08450672B2

公开(公告)日：2013-05-28

申请号：US12751552

申请日：2010-03-31

申请人： Shine Chung ,  Tao-Wen Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Tao-Wen Chung ,  Fu-Lung Hsueh

IPC分类号： H01L27/146 ,  H01L31/101

CPC分类号： H01L27/14609 ,  H01L27/14601 ,  H01L27/14643 ,  H01L31/0352

摘要： An integrated circuit structure includes an image sensor cell, which further includes a photo transistor configured to sense light and to generate a current from the light.

摘要翻译： 集成电路结构包括图像传感器单元，其还包括被配置为感测光并从光产生电流的光电晶体管。

公开(公告)号：US20130126979A1

公开(公告)日：2013-05-23

申请号：US13302335

申请日：2011-11-22

申请人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Kuoyuan (Peter) HSU

发明人： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Kuoyuan (Peter) HSU

IPC分类号： H01L27/13 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L21/823437 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

摘要翻译： 形成集成电路的方法包括在衬底上形成至少一个晶体管。 形成至少一个晶体管包括在衬底上形成栅极电介质结构。 在栅介电结构上形成功函数金属层。 在功函数金属层上形成导电层。 源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。 在衬底上形成至少一个电熔丝。 形成至少一个电熔丝包括在衬底上形成第一半导体层。 在第一半导体层上形成第一硅化物层。

公开(公告)号：US20130082754A1

公开(公告)日：2013-04-04

申请号：US13252498

申请日：2011-10-04

申请人： Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

发明人： Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

IPC分类号： H03L7/08

CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L2207/06

摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

摘要翻译： 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

公开(公告)号：US20130038418A1

公开(公告)日：2013-02-14

申请号：US13206584

申请日：2011-08-10

申请人： Ping-Lin Yang ,  Jun-De Jin ,  Fu-Lung Hsueh ,  Sa-Lly Liu ,  Tong-Chern Ong ,  Chun-Jung Lin ,  Ya-Chen Kao

发明人： Ping-Lin Yang ,  Jun-De Jin ,  Fu-Lung Hsueh ,  Sa-Lly Liu ,  Tong-Chern Ong ,  Chun-Jung Lin ,  Ya-Chen Kao

IPC分类号： H01F38/14 ,  H01F41/00

CPC分类号： H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

摘要： A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

摘要翻译： 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

公开(公告)号：US08324970B2

公开(公告)日：2012-12-04

申请号：US12894903

申请日：2010-09-30

申请人： Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Sally Liu

发明人： Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Sally Liu

IPC分类号： H03F3/04

CPC分类号： H03F3/19 ,  H01L29/78

摘要： A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate.

摘要翻译： 射频放大器电路包括能够接收衬底偏置电压的衬底。 晶体管的源极能够接收源极偏置电压。 晶体管的漏极能够接收漏极偏置电压。 晶体管的栅极位于源极和漏极之间。 射频输入信号耦合到门。 衬底偏置电路提供衬底偏置电压。 衬底偏置电压和源极偏置电压正向偏置由源极和衬底形成的第一二极管。 衬底偏置电压和漏极偏置电压反向偏置由漏极和衬底形成的第二二极管。

公开(公告)号：US08295018B2

公开(公告)日：2012-10-23

申请号：US12843082

申请日：2010-07-26

申请人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC分类号： H03F1/52 ,  H01L27/0288 ,  H03F3/189 ,  H03F2200/255 ,  H03F2200/441 ,  H03F2200/444

摘要： An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad.

摘要翻译： ESD保护电路包括信号焊盘，芯片上的短路分流短截线并且耦合到信号焊盘，芯片上的开路分流短截线并耦合到信号焊盘。

公开(公告)号：US20120264269A1

公开(公告)日：2012-10-18

申请号：US13535090

申请日：2012-06-27

申请人： Po-Yao Ke ,  Tao-Wen Chung ,  Shine Chung ,  Fu-Lung Hsueh

发明人： Po-Yao Ke ,  Tao-Wen Chung ,  Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01L21/8222

CPC分类号： H01L29/73 ,  H01L21/823431

摘要： A method of forming a semiconductor device is provided. The method includes forming a first fin above a substrate, forming a first emitter region in a first portion of the first fin, forming a first collector region in a second portion of the first fin, and forming a first base region in a third portion of the first fin. The third portion of the first fin is disposed underneath a first gate electrode. The method further includes forming a second fin adjacent to the first fin and above the substrate. The second fin is composed of a semiconductor material. The method also includes forming a first base contact over the second fin. The first base contact is coupled to the first base region through the second fin, the substrate, and the first fin.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括在衬底上形成第一鳍片，在第一鳍片的第一部分中形成第一发射极区域，在第一鳍片的第二部分中形成第一集电极区域，并在第三鳍片的第三部分形成第一基底区域 第一个翅膀 第一鳍片的第三部分设置在第一栅电极下方。 该方法还包括形成邻近第一鳍片和衬底上方的第二鳍片。 第二鳍由半导体材料构成。 该方法还包括在第二翅片上形成第一基底接触。 第一基底接触件通过第二鳍片，基底和第一鳍片耦合到第一基底区域。

公开(公告)号：US20120217586A1

公开(公告)日：2012-08-30

申请号：US13035533

申请日：2011-02-25

申请人： Chan-Hong CHERN ,  Fu-Lung HSUEH

发明人： Chan-Hong CHERN ,  Fu-Lung HSUEH

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.

摘要翻译： 形成集成电路的方法包括在衬底上形成至少一个晶体管。 所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。 工作功能金属层设置在第一栅极电介质结构上。 导电层设置在功函数金属层上。 源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。 在衬底上形成至少一个电阻器结构。 所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。 至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

公开(公告)号：US08207775B2

公开(公告)日：2012-06-26

申请号：US12871343

申请日：2010-08-30

申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

IPC分类号： H03L5/00

CPC分类号： H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

摘要： A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

摘要翻译： 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US08193963B2

公开(公告)日：2012-06-05

申请号：US12874462

申请日：2010-09-02

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng-Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng-Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03M1/50

CPC分类号： G04F10/005

摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

摘要翻译： 公开了时间到数字转换（TDC）的方法和装置。 定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。 校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。 被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。