公开(公告)号：US20100133619A1

公开(公告)日：2010-06-03

申请号：US12698449

申请日：2010-02-02

Applicant: Se-Aug JANG ,  Heung-Jae CHO ,  Kwan-Yong LIM ,  Tae-Yoon KIM

Inventor： Se-Aug JANG ,  Heung-Jae CHO ,  Kwan-Yong LIM ,  Tae-Yoon KIM

IPC: H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/66795 ,  H01L29/7851

Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.

Abstract translation: 翅片晶体管包括翅片有源区，覆盖翅片有源区的下部的两个侧壁的隔离层，设置在翅片有源区的表面上的栅极绝缘层，以及设置在栅极绝缘层和栅极绝缘层上的栅极 隔离层，并且具有范围从约4.4eV至约4.8eV的功函数。

公开(公告)号：US20090114981A1

公开(公告)日：2009-05-07

申请号：US12164067

申请日：2008-06-29

Applicant: Min-Gyu SUNG ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Kwan-Yong Lim ,  Se-Aug Jang

Inventor： Min-Gyu SUNG ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Kwan-Yong Lim ,  Se-Aug Jang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/7827

Abstract: In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.

Abstract translation: 在高速垂直沟道晶体管中，在衬底上形成柱结构，栅电极围绕柱结构的下部的外壁; 并且字线在与栅电极的外壁部分接触的方向上延伸。 字线向柱结构的一侧移动，导致晶体管速度增加。

公开(公告)号：US20080277743A1

公开(公告)日：2008-11-13

申请号：US11967133

申请日：2007-12-29

Applicant: Heung-Jae CHO ,  Hong-Seon YANG ,  Se-Aug JANG

Inventor： Heung-Jae CHO ,  Hong-Seon YANG ,  Se-Aug JANG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/28044 ,  H01L21/28114 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/42376 ,  H01L29/66484 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a recess in an area where a gate is to be formed, spacers formed over sidewalls of the recess, and a first gate electrode filling in the recess. The spacers include material having the first work function or insulation material. The first gate electrode includes material having a second work function, wherein the second work function is higher than that of the spacers.

Abstract translation: 半导体器件包括：衬底，其具有在要形成栅极的区域中的凹部;衬垫形成在凹槽的侧壁上;以及填充在凹部中的第一栅电极。 间隔物包括具有第一功函或绝缘材料的材料。 第一栅电极包括具有第二功函数的材料，其中第二功函数高于隔片的功函数。

公开(公告)号：US20080079048A1

公开(公告)日：2008-04-03

申请号：US11862453

申请日：2007-09-27

Applicant: Yong-Soo Kim ,  Hong-Seon Yang ,  Se-Aug Jang ,  Seung-Ho Pyi ,  Kwon Hong ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Min-Gyu Sung ,  Seung-Ryong Lee ,  Tae-Yoon Kim

Inventor： Yong-Soo Kim ,  Hong-Seon Yang ,  Se-Aug Jang ,  Seung-Ho Pyi ,  Kwon Hong ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Min-Gyu Sung ,  Seung-Ryong Lee ,  Tae-Yoon Kim

IPC: H01L27/108 ,  H01L21/3205

CPC classification number: H01L29/66553 ,  H01L27/10876 ,  H01L29/518 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Abstract translation: 一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。 栅极导电层填充灯泡型凹陷区域。 栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

公开(公告)号：US07332755B2

公开(公告)日：2008-02-19

申请号：US11201951

申请日：2005-08-10

Applicant: Se Aug Jang ,  Yong Soo Kim ,  Jae Geun Oh ,  Jae Sung Roh ,  Hyun Chun Sohn

Inventor： Se Aug Jang ,  Yong Soo Kim ,  Jae Geun Oh ,  Jae Sung Roh ,  Hyun Chun Sohn

IPC: H01L29/72

CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

Abstract translation: 存储器件包括从半导体衬底突出的有源区。 在活动区域​​中形成凹部。 在半导体衬底上形成场氧化物层。 栅极电极延伸穿过有源区域同时与凹部重叠。 栅极绝缘层介于栅电极和有源区之间。 源极和漏极区域形成在有源区域中。 如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。 晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

公开(公告)号：US07279388B2

公开(公告)日：2007-10-09

申请号：US11154458

申请日：2005-06-16

Applicant: Yong Soo Kim ,  Se Aug Jang ,  Jae Geun Oh

Inventor： Yong Soo Kim ,  Se Aug Jang ,  Jae Geun Oh

IPC: H01L21/336

CPC classification number: H01L21/823437 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7834

Abstract: Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having active and field regions; performing a channel ion implantation into the substrate; sequentially forming a hard mask film and a photoresist pattern exposing a gate formation region where the channel ion implantation occurred; performing a second, higher concentration channel ion implantation using the photoresist pattern as a mask, forming doped regions in the substrate at the gate formation region and sides; etching a hard mask using the photoresist pattern as a barrier; removing the photoresist pattern; etching the substrate using a portion of the remaining hard mask as a barrier forming a groove; removing the remaining hard mask; forming a gate in the groove where the hard mask was removed; and forming source and drain regions at both sides of the gate.

Abstract translation: 公开了一种用于制造半导体器件中的晶体管的方法，其可以提高器件的刷新特性。 该方法包括：提供具有活性和场区域的硅衬底; 对衬底进行沟道离子注入; 依次形成硬掩模膜和曝光出现沟道离子注入的栅形成区的光致抗蚀剂图案; 使用光致抗蚀剂图案作为掩模进行第二较高浓度的通道离子注入，在栅极形成区域和侧面在衬底中形成掺杂区域; 使用光致抗蚀剂图案作为屏障蚀刻硬掩模; 去除光致抗蚀剂图案; 使用剩余的硬掩模的一部分来蚀刻基板作为形成凹槽的阻挡层; 去除剩余的硬掩模; 在去除硬掩模的槽中形成栅极; 并在栅极的两侧形成源极和漏极区域。

公开(公告)号：US07217624B2

公开(公告)日：2007-05-15

申请号：US11024472

申请日：2004-12-30

Applicant: Kwan-Yong Lim ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Se-Aug Jang ,  Hyun-Chul Sohn

Inventor： Kwan-Yong Lim ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Se-Aug Jang ,  Hyun-Chul Sohn

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7887 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66825 ,  H01L29/788

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

公开(公告)号：US07145207B2

公开(公告)日：2006-12-05

申请号：US11027663

申请日：2004-12-30

Applicant: Hong-Seon Yang ,  Se-Aug Jang ,  Yong-Soo Kim ,  Kwan-Yong Lim ,  Heung-Jae Cho ,  Jae-Geun Oh

Inventor： Hong-Seon Yang ,  Se-Aug Jang ,  Yong-Soo Kim ,  Kwan-Yong Lim ,  Heung-Jae Cho ,  Jae-Geun Oh

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10873 ,  H01L27/10888

Abstract: A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012 ° C.-dyne/cm2.

Abstract translation: 一种半导体存储器件的栅极结构，其能够通过形成硬掩模并将滞后区域保持在一定值内来防止多孔隙生成。 半导体存储器件的栅极结构包括：形成在半导体衬底上的栅绝缘层; 形成在所述栅绝缘层上的栅电极，其中所述栅电极通过堆叠多晶硅层和金属层而形成; 以及形成在所述栅极电极上的硬掩模，其中所述硬掩模和所述栅极电极材料之间的滞后区域等于或小于约2×10 12·达因/ cm 2， 2 。

公开(公告)号：US20060160286A1

公开(公告)日：2006-07-20

申请号：US11385217

申请日：2006-03-20

Applicant: Eung-Rim Hwang ,  Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn

Inventor： Eung-Rim Hwang ,  Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn

IPC: H01L21/338 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/115 ,  H01L29/7886

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

公开(公告)号：US07074661B2

公开(公告)日：2006-07-11

申请号：US10879732

申请日：2004-06-30

Applicant: Heung-Jae Cho ,  Se-Aug Jang ,  Kwan-Yong Lim

Inventor： Heung-Jae Cho ,  Se-Aug Jang ,  Kwan-Yong Lim

IPC: H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L21/823437 ,  H01L29/4941 ,  H01L29/6656

Abstract: Disclosed is a method for fabricating a semiconductor device with a polymetal gate electrode formed by a partial gate recessing process. The method includes the steps of forming a gate structure including a gate dielectric layer, a polysilicon layer, a metal layer, an etch stop layer and a sacrificial layer sequentially formed on a substrate; selectively performing a re-oxidation process to the gate structure; forming a spacer on each sidewall of the gate structure; implanting ions in the substrate for forming source/drain regions; selectively removing the sacrificial layer of the gate structure to form a recess; and filling an insulating hard mask into the recess for use in a self-aligned contact etching process.

Abstract translation: 公开了一种通过部分栅极凹陷工艺形成的具有多金属栅电极的半导体器件的制造方法。 该方法包括以下步骤：形成栅极结构，该栅极结构包括依次形成在衬底上的栅介电层，多晶硅层，金属层，蚀刻停止层和牺牲层; 选择性地对栅极结构进行再氧化处理; 在所述栅极结构的每个侧壁上形成间隔物; 在衬底中注入离子以形成源/漏区; 选择性地去除栅极结构的牺牲层以形成凹陷; 并将绝缘硬掩模填充到凹槽中以用于自对准接触蚀刻工艺。