公开(公告)号：US07508988B2

公开(公告)日：2009-03-24

申请号：US11074080

申请日：2005-03-08

申请人： Junichi Hara ,  Toshio Miyazawa ,  Fumihiro Hasegawa ,  Hideaki Yamagata ,  Hiroaki Nagatsuka

发明人： Junichi Hara ,  Toshio Miyazawa ,  Fumihiro Hasegawa ,  Hideaki Yamagata ,  Hiroaki Nagatsuka

IPC分类号： G06K9/36

CPC分类号： H04N19/187 ,  H04N19/115 ,  H04N19/17 ,  H04N19/37 ,  H04N19/647

摘要： An image processing apparatus includes a receiving mechanism configured to receive a request, from at least one different image processing apparatus connected via a network, for transmission of a codestream generated in a way such that image data is divided into at least one region, each region being hierarchically compressed and stored in the image processing apparatus, a decomposing mechanism configured to decompose a codestream and retrieve the codestream in a component unit, an extracting mechanism configured to extract a target region from the codestream, a primary priority assigning mechanism configured to assign priority to the target region extracted by the extracting mechanism, and a primary transmitting mechanism configured for transmission of the codestream, decomposed in a component unit corresponding to the target region, to the different image processing apparatus requesting transmission of the codestream based on the priority assigned by the primary priority assigning mechanism.

摘要翻译： 一种图像处理装置包括：接收机构，被配置为从经由网络连接的至少一个不同的图像处理装置接收用于传输以使得图像数据被划分为至少一个区域的方式产生的码流的请求，每个区域 被分级压缩并存储在图像处理装置中;分解机构，被配置为分解码流并以分量单元检索码流;提取机构，被配置为从码流中提取目标区域;主要优先级分配机制，被配置为分配优先级 到由提取机构提取的目标区域，以及主要发送机构，被配置为将与目标区域对应的分量单元分解的码流传输到不同的图像处理装置，该图像处理装置根据由 主要优先级分配给我 chanism。

公开(公告)号：US20080316385A1

公开(公告)日：2008-12-25

申请号：US12153508

申请日：2008-05-20

申请人： Mieko Matsumura ,  Toshio Miyazawa ,  Takeshi Sato ,  Yoshiaki Toyota

发明人： Mieko Matsumura ,  Toshio Miyazawa ,  Takeshi Sato ,  Yoshiaki Toyota

IPC分类号： G02F1/1343 ,  G02F1/133

CPC分类号： G02F1/134363 ,  G02F1/13439 ,  G02F1/136213

摘要： Three layers are formed on a TFT substrate SUB 100. The three layers include a first transparent electrode PSL1 131, a second transparent electrode CSL 127 and a third transparent electrode PSL2 132, all of which are laminated in parallel to the substrate surface. Two auxiliary capacitances to a liquid crystal capacitance are formed between the first transparent electrode PSL1 131 and the second transparent electrode CSL 127 and between the second transparent electrode CSL 127 and the third transparent electrode PSL2 132.

摘要翻译： 三层形成在TFT基板SUB100上。三层包括第一透明电极PSL1 131，第二透明电极CSL 127和第三透明电极PSL2 132，它们均与基板表面平行地层叠。 在第一透明电极PSL1 131和第二透明电极CSL 127之间以及第二透明电极CSL 127和第三透明电极PSL2 132之间形成液晶电容的两个辅助电容。

公开(公告)号：US20080278650A1

公开(公告)日：2008-11-13

申请号：US12100493

申请日：2008-04-10

申请人： Hisayoshi KAJIWARA ,  Norio Mamba ,  Toshio Miyazawa ,  Masahiro Maki

发明人： Hisayoshi KAJIWARA ,  Norio Mamba ,  Toshio Miyazawa ,  Masahiro Maki

IPC分类号： G02F1/136

CPC分类号： G09G3/3696 ,  G09G2300/0408 ,  G09G2310/0289

摘要： An inverter includes an input inverter having a high-resistance load and a first transistor and an output buffer including second and third transistors coupled in series. A power supply voltage is provided to satisfy an inequality VDD1>VDD2+Vth where VDD1 is the power supply voltage of the input inverter, VDD2 is the power supply voltage of the output buffer, and Vth is the threshold voltage of the transistors. Use of the high-resistance load allows an output waveform to rise and fall quickly, as well as reduces current consumption.

摘要翻译： 逆变器包括具有高电阻负载的输入反相器和第一晶体管，以及包括串联耦合的第二和第三晶体管的输出缓冲器。 提供电源电压以满足不等式VDD 1> VDD 2+ Vth，其中VDD 1是输入反相器的电源电压，VDD 2是输出缓冲器的电源电压，Vth是阈值电压 晶体管。 使用高电阻负载允许输出波形快速上升和下降，以及降低电流消耗。

公开(公告)号：US07450773B2

公开(公告)日：2008-11-11

申请号：US10758638

申请日：2004-01-14

申请人： Yasuyuki Nomizu ,  Hiroyuki Sakuyama ,  Junichi Hara ,  Nekka Matsuura ,  Takanori Yano ,  Taku Kodama ,  Toshio Miyazawa ,  Yasuyuki Shinkai ,  Takayuki Nishimura

发明人： Yasuyuki Nomizu ,  Hiroyuki Sakuyama ,  Junichi Hara ,  Nekka Matsuura ,  Takanori Yano ,  Taku Kodama ,  Toshio Miyazawa ,  Yasuyuki Shinkai ,  Takayuki Nishimura

IPC分类号： G06K9/36 ,  G06K9/46

CPC分类号： H04N19/40 ,  H04N19/162 ,  H04N19/428 ,  H04N19/60 ,  H04N19/63

摘要： An image processing apparatus includes an image data acquisition unit to acquire first encoded image data of a first data size, an image data creation unit to create a second encoded image data of a second, smaller data size than the first data size from the first encoded image data, a display unit to display an image corresponding to the second encoded image data in a displayunit, an editing unit to accept an edit operation to the image displayed in the display unit and for applying an edit processing corresponding to the edit operation to the first encoded image data, and an edit-result manifesting unit to manifest a result of the edit processing to the second encoded image data.

摘要翻译： 一种图像处理装置包括：图像数据获取单元，用于获取第一数据大小的第一编码图像数据;图像数据创建单元，用于从第一编码单元创建第二编码图像数据，该第二编码图像数据比第一数据大小小 图像数据，用于在显示单元中显示与第二编码图像数据相对应的图像的显示单元，编辑单元，接受对显示单元中显示的图像的编辑操作，以及将与编辑操作相对应的编辑处理应用于 第一编码图像数据，以及编辑结果显示单元，用于向第二编码图像数据显示编辑处理的结果。

公开(公告)号：US07409060B2

公开(公告)日：2008-08-05

申请号：US10716429

申请日：2003-11-20

申请人： Yasuyuki Nomizu ,  Hiroyuki Sakuyama ,  Junichi Hara ,  Nekka Matsuura ,  Takanori Yano ,  Taku Kodama ,  Toshio Miyazawa ,  Yasuyuki Shinkai ,  Takayuki Nishimura

发明人： Yasuyuki Nomizu ,  Hiroyuki Sakuyama ,  Junichi Hara ,  Nekka Matsuura ,  Takanori Yano ,  Taku Kodama ,  Toshio Miyazawa ,  Yasuyuki Shinkai ,  Takayuki Nishimura

IPC分类号： H04N7/167 ,  H04L9/00 ,  G06K9/00 ,  B42D15/00

CPC分类号： G06T1/0057 ,  G06T2201/0052 ,  H04N1/32154 ,  H04N1/3217 ,  H04N1/32277 ,  H04N1/32283 ,  H04N1/32309 ,  H04N21/8153 ,  H04N21/8358

摘要： A digital watermarking technique is disclosed, in which image data are converted to frequency components through discrete wavelet transform and quantized into a set of quantized coefficients, which are then divided into a plurality of blocks. A digital watermark is embedded in the quantized coefficients by performing ON/OFF adjustment of bit information, such that the relation between natural number T and the bit information defined by N (N is an even number) significant bits Qnm (x, y) of the m-th bit plane of the n-th block satisfies the ON state represented by equation (1), or the OFF state represented by equation (2), depending on whether the hash value of the n-th block is odd or even. Then the quantized coefficients are encoded to produce a code stream.

摘要翻译： 公开了一种数字水印技术，其中图像数据通过离散小波变换转换成频率分量，并量化为一组量化系数，然后将其分成多个块。 通过执行比特信息的ON / OFF调整，将数字水印嵌入到量化系数中，使得自然数T与由N（N是偶数）定义的比特信息之间的关系有效比特Qnm（x，y） 根据第n个块的散列值是奇数还是偶数，第n个块的第m位平面满足由等式（1）表示的ON状态或由等式（2）表示的OFF状态 。 然后对量化的系数进行编码以产生码流。

公开(公告)号：US20070268227A1

公开(公告)日：2007-11-22

申请号：US11797033

申请日：2007-04-30

申请人： Toshio Miyazawa ,  Iwao Takemoto ,  Atsushi Hasegawa ,  Masashiro Maki ,  Kazutaka Goto

发明人： Toshio Miyazawa ,  Iwao Takemoto ,  Atsushi Hasegawa ,  Masashiro Maki ,  Kazutaka Goto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3659 ,  G09G3/3688 ,  G09G3/3696 ,  G09G5/39 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28 ,  H01L27/12 ,  H01L27/124 ,  H01L29/42384

摘要： A display device includes a dynamic ratio less shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratio less shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

摘要翻译： 显示装置包括动态比例少移位寄存器，其以稳定的方式操作并且可以扩展设计的自由度。 在具有在衬底表面上由p-Si制成的半导体层的薄膜晶体管的动态比较少的移位寄存器中，通过电容元件将成为浮置状态的节点连接到固定电位。

公开(公告)号：US20070229553A1

公开(公告)日：2007-10-04

申请号：US11753942

申请日：2007-05-25

申请人： TOSHIO MIYAZAWA

发明人： TOSHIO MIYAZAWA

IPC分类号： G09G5/10

CPC分类号： G09G3/2011 ,  G09G3/3685 ,  G09G3/3688 ,  G09G2310/027

摘要： A display device including: a plurality of pixels arranged in a matrix array; a selector circuit for selecting one from a plurality of rows of pixels in said matrix array; and a video signal supplying circuit for supplying a video signal to each of pixels in said selected row in synchronism with said selection of said selected row, wherein said video signal supplying circuit is provided with a transfer-data processing section for generating a data signal at a time assigned to a gray scale level, in accordance with n-bit data information representing said gray scale level, and a gray-scale voltage selector circuit section for supplying as said video signal, a voltage signal selected from among a plurality of gray-scale voltages, based upon said time associated with said data signal, said plurality of gray-scale voltages being successively selected.

摘要翻译： 一种显示装置，包括：排列成矩阵阵列的多个像素; 选择器电路，用于从所述矩阵阵列中的多行像素中选择一个; 以及视频信号提供电路，用于与所选择的行的所述选择同步地向视频信号提供所述选定行中的每个像素，其中所述视频信号提供电路设置有传送数据处理部分，用于产生数据信号 根据表示所述灰度级的n位数据信息，分配给灰度级的时间，以及灰度级电压选择器电路部分，用于将所述视频信号中的多个灰度级选择电压信号， 基于与所述数据信号相关联的所述时间，所述多个灰度级电压被连续地选择。

公开(公告)号：US07274625B1

公开(公告)日：2007-09-25

申请号：US11700876

申请日：2007-02-01

申请人： Katsumi Matsumoto ,  Kozo Yasuda ,  Hiroshi Kageyama ,  Hideo Sato ,  Toshio Miyazawa

发明人： Katsumi Matsumoto ,  Kozo Yasuda ,  Hiroshi Kageyama ,  Hideo Sato ,  Toshio Miyazawa

IPC分类号： G04C17/00 ,  H03K3/03 ,  G09G3/20

CPC分类号： G09G3/3611 ,  G09G3/20

摘要： An oscillator circuit includes (2n+1) inverters connected in series when n is a natural number, an integrator circuit having an input terminal connected to an output terminal of a (2n+1)-th inverter and an output terminal connected to an input terminal of a first inverter, first and second p-type transistors connected in series between the input terminal of the first inverter and a first reference potential, and first and second n-type transistors connected in series between the input terminal of the first inverter and a second reference potential. An output voltage of a j-th inverter is applied to control electrodes of the first p-type transistor and the first n-type transistor. An output voltage of a k-th inverter is applied to control-electrodes of the second p-type transistor and the second n-type transistor. Symbol j is an odd number, k is an even number, and j

摘要翻译： 振荡器电路包括当n为自然数时串联连接的（2n + 1）个反相器，具有连接到第（2n + 1）个反相器的输出端的输入端的积分器电路和连接到输入端的输出端 串联连接在第一反相器的输入端和第一参考电位之间的第一和第二p型晶体管，以及串联连接在第一反相器的输入端和第一反相器的第一和第二p型晶体管之间的第一和第二p型晶体管， 第二个参考电位。 将第j个反相器的输出电压施加到第一p型晶体管和第一n型晶体管的控制电极。 第k个反相器的输出电压被施加到第二p型晶体管和第二n型晶体管的控制电极。 符号j是奇数，k是偶数，并且满足j

公开(公告)号：US20070182689A1

公开(公告)日：2007-08-09

申请号：US11670060

申请日：2007-02-01

申请人： Toshio Miyazawa ,  Hideo Sato

发明人： Toshio Miyazawa ,  Hideo Sato

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2300/0465 ,  G09G2300/0852 ,  G09G2320/10 ,  G09G2330/021

摘要： In a display device used in a compact mobile apparatus that uses a battery or the like as the poser supply, the display device consumes less power even when the display state is not switched for a long period of time. A memory element is provided in each pixel, but the number of the parts does not increase and the aperture ratio is maintained at a high level.A low power-consumption liquid crystal display device is achieved by providing the memory element in each pixel and transferring no image signal. The voltage held in the pixel memory in the liquid crystal display panel is used to generate an alternating drive signal in the pixel. Even when the image signal is not rewritten, the alternating drive avoids liquid crystal degradation and performs display operations. The simply configured memory element allows a liquid crystal display device without aperture ratio penalty to be achieved.

摘要翻译： 在使用电池等作为配置电源的紧凑型移动装置中使用的显示装置中，即使显示状态长时间不切换，显示装置也消耗较少的电力。 在每个像素中提供存储元件，但是部件的数量不增加，并且孔径比保持在高水平。 通过在每个像素中提供存储元件并且不传输图像信号来实现低功耗液晶显示装置。 保持在液晶显示面板中的像素存储器中的电压用于在像素中产生交替的驱动信号。 即使图像信号未被重写，交替驱动也避免液晶退化并进行显示操作。 简单配置的存储元件允许实现无孔径比损坏的液晶显示装置。

公开(公告)号：US20070182679A1

公开(公告)日：2007-08-09

申请号：US11700876

申请日：2007-02-01

申请人： Katsumi Matsumoto ,  Kozo Yasuda ,  Hiroshi Kageyama ,  Hideo Sato ,  Toshio Miyazawa

发明人： Katsumi Matsumoto ,  Kozo Yasuda ,  Hiroshi Kageyama ,  Hideo Sato ,  Toshio Miyazawa

IPC分类号： G09G3/34

CPC分类号： G09G3/3611 ,  G09G3/20

摘要： An oscillator circuit includes (2n+1) inverters connected in series when n is a natural number, an integrator circuit having an input terminal connected to an output terminal of a (2n+1)-th inverter and an output terminal connected to an input terminal of a first inverter, first and second p-type transistors connected in series between the input terminal of the first inverter and a first reference potential, and first and second n-type transistors connected in series between the input terminal of the first inverter and a second reference potential. An output voltage of a j-th inverter is applied to control electrodes of the first p-type transistor and the first n-type transistor. An output voltage of a k-th inverter is applied to control electrodes of the second p-type transistor and the second n-type transistor. Symbol j is an odd number, k is an even number, and j

摘要翻译： 振荡器电路包括当n为自然数时串联连接的（2n + 1）个反相器，具有连接到第（2n + 1）个反相器的输出端的输入端的积分器电路和连接到输入端的输出端 串联连接在第一反相器的输入端和第一参考电位之间的第一和第二p型晶体管，以及串联连接在第一反相器的输入端和第一反相器的第一和第二p型晶体管之间的第一和第二p型晶体管， 第二个参考电位。 将第j个反相器的输出电压施加到第一p型晶体管和第一n型晶体管的控制电极。 第k个反相器的输出电压被施加到第二p型晶体管和第二n型晶体管的控制电极。 符号j是奇数，k是偶数，并且满足j