公开(公告)号：US20160250305A1

公开(公告)日：2016-09-01

申请号：US14929641

申请日：2015-11-02

Applicant: Ajay Kumar

Inventor： Ajay Kumar

IPC: A61K39/00 ,  A61K31/4741

CPC classification number: A61K39/00 ,  A61K31/4741

Abstract: Disclosed is the novel use of some Aza-podophyllotoxin derivatives (AZPs) for modulation of the immune system (immunomodulation), including a method for modulating an immune response comprising administering to a subject an effective amount of at least one Aza-podophyllotoxin derivative of general formula wherein A-ring is selected from the group consisting of 1,3-dioxolane, cyclopentane, 1,4-dioxane, one methoxy, two methoxys, and ethyl; and wherein E-ring is selected from the group consisting of dimethoxyanisole, veratrol, anisole, benzene, syringol, bromobenzene, chlorobenzene, 1,2-dichlorobenzene, 2,3-dimethoxybenzene, 3,4,5-trimethoxybenzene.

Abstract translation: 公开了一些甲氮鬼臼毒素衍生物（AZP）用于调节免疫系统（免疫调节）的新用途，包括调节免疫应答的方法，包括向受试者施用有效量的至少一种一般的氮杂鬼臼毒素衍生物 其中A环选自1,3-二氧戊环，环戊烷，1,4-二恶烷，一甲氧基，二甲氧基和乙基; 其中E环选自二甲氧基苯甲醚，藜芦醇，苯甲醚，苯，丁腈橡胶，溴苯，氯苯，1,2-二氯苯，2,3-二甲氧基苯，3,4,5-三甲氧基苯。

公开(公告)号：US09355907B1

公开(公告)日：2016-05-31

申请号：US14589918

申请日：2015-01-05

Applicant: Wei-Sheng Lei ,  Jungrae Park ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Jungrae Park ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/78 ,  H01L23/28 ,  H01L21/82 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/82 ,  B23K26/364 ,  B23K2103/56 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/02076 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a line shaped laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用线形激光束轮廓激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US20160086851A1

公开(公告)日：2016-03-24

申请号：US14490598

申请日：2014-09-18

Applicant: Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/78 ,  B23K26/36 ,  H01L21/67 ,  H01J37/32 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/78 ,  B23K26/364 ,  H01J37/32889 ,  H01J2237/335 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67207

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an adaptive optics-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用自适应光学控制激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09263308B2

公开(公告)日：2016-02-16

申请号：US14190024

申请日：2014-02-25

Applicant: Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/683 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/67207 ,  B23K26/0624 ,  B23K26/064 ,  B23K26/364 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

Abstract: Methods of dicing substrates having a plurality of ICs are disclosed. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer is washed off.

Abstract translation: 公开了具有多个IC的切割衬底的方法。 一种方法包括在半导体衬底上形成包含水溶性材料层的掩模。 用飞秒激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使IC之间的衬底的区域暴露。 然后将衬底通过图案化掩模中的间隙进行蚀刻，以对IC进行分离，并将水溶性材料层冲洗掉。

公开(公告)号：US20150311107A1

公开(公告)日：2015-10-29

申请号：US14542422

申请日：2014-11-14

Applicant: Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/683 ,  H01L21/3065 ,  B32B3/26 ,  H01L21/67 ,  B32B37/00 ,  B32B37/22 ,  H01L21/78 ,  H01L21/308

CPC classification number: H01L21/6836 ,  B32B3/266 ,  B32B37/0076 ,  B32B37/22 ,  B32B2307/202 ,  B32B2457/14 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.

Abstract translation: 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 在一个示例中，减少支撑的半导体晶片中的边缘翘曲的方法包括将半导体晶片的背面粘附到包括安装在载带上方的带框架的基板载体的载带的内部。 该方法还包括将粘合带粘附到半导体晶片的正面以及衬底载体的至少一部分。 胶带包括露出半导体晶片正面的内部区域的开口。

公开(公告)号：US20150303111A1

公开(公告)日：2015-10-22

申请号：US14543747

申请日：2014-11-17

Applicant: Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/268

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12041 ,  H01L2224/11 ,  H01L2924/00

Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.

Abstract translation: 描述了具有背面焊料凸块的晶片的混合激光划片和等离子体蚀刻切割工艺的方法。 例如，在其前侧具有集成电路的半导体晶片的切割方法和背面的金属凸块的相应阵列包括在半导体晶片的背面施加切割带，该切割带覆盖金属凸块的阵列 。 该方法还包括在半导体晶片的正面上形成掩模，该掩模覆盖集成电路。 该方法还涉及通过激光划线工艺在半导体晶片的正面上形成刻划线，在掩模中形成划线并在集成电路之间。 该方法还包括通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，掩模在等离子体蚀刻期间保护集成电路。

公开(公告)号：US20150294892A1

公开(公告)日：2015-10-15

申请号：US14563901

申请日：2014-12-08

Applicant: Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L21/6836 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/561 ,  H01L21/563 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67207 ,  H01L21/78 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods and systems for forming water soluble masks by dry film lamination are described. Also described are methods of wafer dicing, including formation of a water soluble mask by dry film lamination. In one embodiment, a method involves moisturizing an inner area of a water soluble dry film. The method involves stretching the water soluble dry film over a surface of the semiconductor wafer, and attaching the moistened inner area of the stretched film to the surface of the semiconductor wafer. A method of wafer dicing may further involve patterning the water soluble dry film, exposing regions of the semiconductor wafer between the ICs, and etching the semiconductor wafer through gaps in the patterned water soluble dry film.

Abstract translation: 描述了通过干膜层压形成水溶性掩模的方法和系统。 还描述了晶片切割的方法，包括通过干膜层压形成水溶性掩模。 在一个实施方案中，一种方法涉及保湿水溶性干膜的内部区域。 该方法包括在半导体晶片的表面上拉伸水溶性干膜，并将拉伸膜的湿润内部区域附着到半导体晶片的表面。 晶片切割的方法还可以包括图案化水溶性干膜，暴露半导体晶片在IC之间的区域，以及通过图案化的水溶性干膜中的间隙蚀刻半导体晶片。

公开(公告)号：US09142459B1

公开(公告)日：2015-09-22

申请号：US14320426

申请日：2014-06-30

Applicant: Prabhat Kumar ,  Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

Inventor： Prabhat Kumar ,  Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves applying an adhesive layer to a front side of the semiconductor wafer. A mask layer is laminated onto the front side of the semiconductor wafer, the mask layer covering and protecting the integrated circuits. The adhesive layer adheres the mask layer to the front side of the semiconductor wafer. The mask layer is patterned with a laser scribing process to provide gaps in the mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the mask layer to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括将粘合剂层施加到半导体晶片的正面。 掩模层被层叠在半导体晶片的前侧，掩模层覆盖并保护集成电路。 粘合剂层将掩模层粘附到半导体晶片的正面。 通过激光划线工艺对掩模层进行构图，以在掩模层中提供间隙，在半导体晶片的间隙暴露在集成电路之间。 通过掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09130057B1

公开(公告)日：2015-09-08

申请号：US14320405

申请日：2014-06-30

Applicant: Prabhat Kumar ,  Wei-Sheng Lei ,  James Papanu ,  Brad Eaton ,  Ajay Kumar

Inventor： Prabhat Kumar ,  Wei-Sheng Lei ,  James Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/822 ,  H01L21/67 ,  B23K26/00 ,  B26D9/00

CPC classification number: B26D9/00 ,  B23K26/0624 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/50 ,  B23K2103/54 ,  B26D3/06 ,  B28D5/022 ,  H01L21/67092 ,  H01L21/78

Abstract: A method and system of hybrid dicing using a blade and laser are described. In one embodiment, a method involves focusing a laser beam inside the substrate in regions between the integrated circuits, inducing defects inside the substrate in the regions. The method also involves forming a groove on a surface of the substrate with a blade saw in the regions. The method further involves singulating the integrated circuits at the regions with the induced defects and the groove. In one embodiment, a system includes a laser module configured to focus a laser beam inside the substrate in regions between the integrated circuits, inducing defects inside the substrate in the regions. A blade grooving module is configured to form a groove in a surface of the substrate with a blade saw in the regions.

Abstract translation: 描述了使用刀片和激光器的混合切割的方法和系统。 在一个实施例中，一种方法包括将集成电路之间的区域内的激光束聚焦在衬底内，从而在区域内的衬底内引起缺陷。 该方法还涉及在该区域中具有刀片锯的基板的表面上形成凹槽。 该方法还涉及在具有感应缺陷和凹槽的区域处分离集成电路。 在一个实施例中，系统包括激光模块，该激光模块被配置为将集成电路之间的区域内的激光束聚焦在衬底内，从而在该区域内的衬底内引起缺陷。 刀片切槽模块被配置为在所述区域中具有刀片锯的基板的表面中形成凹槽。

公开(公告)号：US09129904B2

公开(公告)日：2015-09-08

申请号：US13161026

申请日：2011-06-15

Applicant: Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

Inventor： Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/28 ,  H01L21/308 ,  B23K26/06 ,  H01L21/67 ,  B23K26/36 ,  B23K26/40 ,  H01L21/78

CPC classification number: H01L21/3086 ,  B23K26/06 ,  B23K26/0622 ,  B23K26/0624 ,  B23K26/0626 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a pulse train laser scribing process using multiple-pulse bursts to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 掩模由覆盖和保护集成电路的层组成。 使用多脉冲脉冲串的脉冲串激光划线方法对掩模进行构图，以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。