公开(公告)号：US20140217420A1

公开(公告)日：2014-08-07

申请号：US14251634

申请日：2014-04-13

申请人： Ananda H. Kumar

发明人： Ananda H. Kumar

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/04

CPC分类号： H01L21/02282 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/2003 ,  H01L33/007

摘要： This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefitting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.

摘要翻译： 本文件描述了在产品硅晶片上制造的陶瓷稳定层的制造和使用，以便于其用作制造氮化镓膜的基板。 形成陶瓷层，然后附着到单晶硅衬底上以形成与GaN相当的热膨胀系数的复合硅衬底。 通过本发明制备的复合硅衬底独特地适合用作无裂纹氮化镓膜的生长衬底，受益于通过选择具有比硅和氮化镓的热膨胀系数更高的系数热膨胀的陶瓷而产生的压应力。

公开(公告)号：US08697541B1

公开(公告)日：2014-04-15

申请号：US13337045

申请日：2011-12-23

申请人： Ananda H. Kumar

发明人： Ananda H. Kumar

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/02282 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/2003 ,  H01L33/007

摘要： This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefiting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.

摘要翻译： 本文件描述了在产品硅晶片上制造的陶瓷稳定层的制造和使用，以便于其用作制造氮化镓膜的基板。 形成陶瓷层，然后附着到单晶硅衬底上以形成与GaN相当的热膨胀系数的复合硅衬底。 通过本发明制备的复合硅衬底独特地适合用作无裂纹氮化镓膜的生长衬底，受益于通过选择具有比硅和氮化镓的热膨胀系数更高的系数热膨胀的陶瓷而产生的压应力。

公开(公告)号：US08691470B2

公开(公告)日：2014-04-08

申请号：US12292078

申请日：2008-11-12

申请人： Ananda H. Kumar ,  Dien Nguyen ,  Martin Janousek ,  Tad Armstrong

发明人： Ananda H. Kumar ,  Dien Nguyen ,  Martin Janousek ,  Tad Armstrong

IPC分类号： C03C8/00 ,  H01M2/08 ,  H01M2/14

CPC分类号： H01M8/0286 ,  C03C8/02 ,  C03C8/24 ,  H01M8/0282 ,  H01M8/1246 ,  H01M2008/1293 ,  Y02E60/50

摘要： A seal composition includes a first alkaline earth metal oxide, a second alkaline earth metal oxide which is different from the first alkaline earth metal oxide, aluminum oxide, and silica in an amount such that molar percent of silica in the composition is at least five molar percent greater than two times a combined molar percent of the first alkaline earth metal oxide and the second alkaline earth metal oxide. The composition is substantially free of boron oxide and phosphorus oxide. The seal composition forms a glass ceramic seal which includes silica containing glass cores located in a crystalline matrix comprising barium aluminosilicate, and calcium aluminosilicate crystals located in the glass cores.

摘要翻译： 密封组合物包括第一碱土金属氧化物，与第一碱土金属氧化物不同的第二碱土金属氧化物，氧化铝和二氧化硅，其量使得组合物中二氧化硅的摩尔百分比为至少五摩尔 百分比大于第一碱土金属氧化物和第二碱土金属氧化物的组合摩尔百分数的两倍。 该组合物基本上不含氧化硼和氧化磷。 密封组合物形成玻璃陶瓷密封件，其包括位于包括硅铝酸钡的晶体基质中的含二氧化硅的玻璃核心和位于玻璃核心中的硅铝酸钙晶体。

公开(公告)号：US08030119B2

公开(公告)日：2011-10-04

申请号：US12399248

申请日：2009-03-06

申请人： Tirunelveli S. Ravi ,  Ananda H. Kumar ,  Ashish Asthana

发明人： Tirunelveli S. Ravi ,  Ananda H. Kumar ,  Ashish Asthana

IPC分类号： H01L21/00

CPC分类号： H01L31/1876 ,  H01L21/68728 ,  H01L31/048 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/50 ,  Y02E10/547 ,  Y02P70/521

摘要： A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

摘要翻译： 公开了一种制造光伏（PV）电池板的方法，其中所有PV电池同时形成在固定在基座上的单晶硅母晶片的二维阵列上。 在母晶片的表面上阳极氧化多孔硅分离层。 然后使多孔膜平滑以形成用于外延膜生长的合适表面。 使用外延反应器来生长形成PV电池结构的n型和p型膜。 与n层和p层的接触被沉积，然后将玻璃层粘合到PV电池阵列上。 然后通过剥离运动将多孔硅膜分离穿过所有附着在上面的细胞，然后在PV电池阵列上附加强化层。 母晶片的阵列可以重复使用多次，从而减少完成的太阳能电池板的材料成本。

公开(公告)号：US20100090339A1

公开(公告)日：2010-04-15

申请号：US12558486

申请日：2009-09-11

申请人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

发明人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

IPC分类号： H01L23/48 ,  H05K1/11

CPC分类号： H01L21/486 ,  G01R1/0491 ,  G01R3/00 ,  G01R31/2601 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00014

摘要： This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.

公开(公告)号：US20100068837A1

公开(公告)日：2010-03-18

申请号：US12558490

申请日：2009-09-11

申请人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

发明人： Ananda H. Kumar ,  Ashish Asthana ,  Farooq Quadri

IPC分类号： H01L21/66 ,  H01L21/768

CPC分类号： H01L21/486 ,  G01R1/0491 ,  G01R3/00 ,  G01R31/2601 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00014

摘要： This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.

摘要翻译： 本文件描述了具有一层或多层内部厚膜金属导体图案的多层陶瓷衬底的制造和使用，其中与衬底的一个或两个主表面相交的任何或全部金属通孔延伸出 用于制造柔性，暂时或永久互连的表面到电子部件的端子。 这种结构对于半导体器件的晶片探测和封装是有用的。 在一些实施例中，这样的结构被证明可用于同时测试半导体晶片上的多个器件，或用于将多个衬底组装到晶片上，以实现晶片上的管芯的测试和封装。 在本发明的另一个实施例中，具有厚膜金属导体的单层或多层陶瓷互连结构恰好在产品晶片上制造，以便于在晶片上经济地测试和封装管芯。

公开(公告)号：US06490146B2

公开(公告)日：2002-12-03

申请号：US09929806

申请日：2001-08-13

申请人： You Wang ,  Shamouil Shamouilian ,  Arnold Kholodenko ,  Alexander M. Veytser ,  Surinder S. Bedi ,  Kadthala R. Narendrnath ,  Semyon L. Kats ,  Dennis S. Grimard ,  Wing L. Cheng ,  Ananda H. Kumar

发明人： You Wang ,  Shamouil Shamouilian ,  Arnold Kholodenko ,  Alexander M. Veytser ,  Surinder S. Bedi ,  Kadthala R. Narendrnath ,  Semyon L. Kats ,  Dennis S. Grimard ,  Wing L. Cheng ,  Ananda H. Kumar

IPC分类号： H01G2300

CPC分类号： C04B37/026 ,  C04B37/006 ,  C04B37/021 ,  C04B2237/121 ,  C04B2237/122 ,  C04B2237/123 ,  C04B2237/124 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/348 ,  C04B2237/36 ,  C04B2237/365 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/401 ,  C04B2237/402 ,  C04B2237/403 ,  C04B2237/406 ,  C04B2237/407 ,  C04B2237/61 ,  C04B2237/62 ,  C04B2237/64 ,  C04B2237/74 ,  H01L21/6831 ,  H01L21/6833

摘要： An electrostatic chuck for holding a substrate has an electrostatic member having a dielectric covering an electrode that is chargeable to electrostatically hold the substrate. The bond layer has a metal layer that is infiltrated or brazed between the electrostatic member and the base. The base may be a composite of a ceramic and metal, the composite having a coefficient of thermal expansion within about ±30% of a coefficient of thermal expansion of the electrostatic member. The base may also have a heater.

公开(公告)号：US06440221B2

公开(公告)日：2002-08-27

申请号：US09082430

申请日：1998-05-20

申请人： Shamouil Shamouilian ,  Ananda H. Kumar ,  Kadthala R. Narendrnath ,  Eric Farahmand E Askarinam ,  Edwin C. Weldon ,  Michael Rice ,  Kenneth S. Collins

发明人： Shamouil Shamouilian ,  Ananda H. Kumar ,  Kadthala R. Narendrnath ,  Eric Farahmand E Askarinam ,  Edwin C. Weldon ,  Michael Rice ,  Kenneth S. Collins

IPC分类号： C23C1600

CPC分类号： H01J37/32458 ,  H01J37/321 ,  H01J37/32165 ,  H01J37/32522 ,  H01L21/6831

摘要： A temperature control system 145 is used to control the temperature of a process chamber 25 during processing of a semiconductor substrate 70. The temperature control system 145 comprises a heat exchanger plate 155 for removing heat from the chamber 25, and a heat transfer member 158 for conducting heat to the heat exchanger plate 155. The heat transfer member 158 comprises a lower heat conduction surface 205 bonded to an external surface of the chamber 25, and an upper heat transmitting surface 210 thermally coupled to the heat exchanger plate 155. Preferably, the temperature control assembly comprises a heater 150 for heating the chamber 25, and a computer control system 165 for regulating the heat removed by the heat exchanger plate 155 as well as the heat supplied by the heater 150, to maintain the chamber 25 at substantially uniform temperatures.

摘要翻译： 温度控制系统145用于在半导体衬底70的加工期间控制处理室25的温度。温度控制系统145包括用于从腔室25除去热量的热交换器板155和用于 向热交换器板155传导热量。传热构件158包括结合到室25的外表面的下导热表面205和热耦合到热交换器板155的上传热表面210.优选地， 温度控制组件包括用于加热室25的加热器150和用于调节由热交换器板155移除的热量的计算机控制系统165以及由加热器150供应的热量，以将室25保持在基本均匀的温度 。

公开(公告)号：US06370006B1

公开(公告)日：2002-04-09

申请号：US09506423

申请日：2000-02-17

申请人： Ananda H. Kumar ,  Kadthala Narendrnath ,  Shamouil Shamouilian

发明人： Ananda H. Kumar ,  Kadthala Narendrnath ,  Shamouil Shamouilian

IPC分类号： H02N1300

CPC分类号： H01L21/67109 ,  H01L21/6831 ,  H01L21/6833 ,  H02N13/00

摘要： An electrostatic chuck and a process of manufacturing an electrostatic chuck for supporting a semiconductor wafer during wafer processing and for providing a plurality of gas inlet channels extending through the chuck and through which thermal transfer gas can be supplied to the back side of the wafer to enhance the thermal transfer between the wafer and the chuck, embedding a plurality of inserts in a ceramic electrostatic chuck, each insert comprising a matrix of the ceramic of which the electrostatic chuck is made and a plurality of removable elongate members, and removing the elongate members to form a plurality of elongate holes providing the plurality of gas inlet channels.

摘要翻译： 一种静电卡盘和制造用于在晶片加工期间支撑半导体晶片的静电卡盘的工艺，以及用于提供延伸穿过卡盘的多个气体入口通道，并且热传递气体可以通过该导入通道提供到晶片的背面以增强 在晶片和卡盘之间的热传递，将多个插入件嵌入陶瓷静电卡盘中，每个插入件包括其上形成有静电卡盘的陶瓷基体和多个可移除的细长构件，并且将细长构件移除到 形成多个提供多个气体入口通道的细长孔。

公开(公告)号：US06267839B1

公开(公告)日：2001-07-31

申请号：US09229509

申请日：1999-01-12

申请人： Shamouil Shamouilian ,  Ananda H. Kumar ,  Arnold Kholodenko

发明人： Shamouil Shamouilian ,  Ananda H. Kumar ,  Arnold Kholodenko

IPC分类号： C23C1600

CPC分类号： B23Q3/154 ,  H01L21/6833 ,  Y10T279/23

摘要： A susceptor for a wafer support of a semiconductor processing chamber having multiple parallel electrical contacts between an RF electrode and a thick robust electrode near a bottom of the susceptor. The thick robust electrode has a low resistance and, therefore, evenly distributes RF power over its area. The multiple parallel contacts ensure that the RF power is also uniformly distributed across an area of the RF electrode. A plurality of electrically conductive vias extending between the robust electrode and the RF electrode make a plurality of parallel electrical contacts therebetween. Generally, the robust electrode is attached to a bottom side of the susceptor and is aligned substantially parallel to the RF electrode. An insulator plate is attached to a bottom of the susceptor for electrically isolating the robust electrode for the pedestal.

摘要翻译： 用于半导体处理室的晶片支架的感受体，其在RF电极和靠近基座的底部的厚坚固电极之间具有多个平行的电触点。 厚坚固的电极具有低电阻，因此在其区域上均匀分布RF功率。 多个并联触点确保RF功率也均匀分布在RF电极的一个区域上。 在坚固电极和RF电极之间延伸的多个导电通孔在它们之间形成多个平行的电接触。 通常，坚固的电极附接到基座的底侧，并且基本上平行于RF电极排列。 绝缘板连接到基座的底部，用于电绝缘基座的坚固电极。