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102 条记录 (耗时 0.038 秒)

    Updating a switch software image in a distributed fabric protocol (DFP) switching network
    81.
    发明授权
    Updating a switch software image in a distributed fabric protocol (DFP) switching network 有权
    在分布式架构协议（DFP）交换网络中更新交换机软件映像

    公开(公告)号：US08717874B2

    公开(公告)日：2014-05-06

    申请号：US13595047

    申请日：2012-08-27

    申请人： Nirapada Ghosh ,  Dayavanti G Kamath ,  Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy Pandey

    发明人： Nirapada Ghosh ,  Dayavanti G Kamath ,  Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy Pandey

    IPC分类号： G01R31/08

    CPC分类号： H04L41/0816 ,  H04L41/082

    摘要： A switching network has a plurality of switches including at least a switch and a managing master switch. At the managing master switch, a first capability vector (CV) is received from the switch. The managing master switch determines whether the first CV is compatible with at least a second CV in a network membership data structure that records CVs of multiple switches in the switching network. In response to detecting an incompatibility, the managing master switch initiates an image update to an image of the switch. In response to a failure of the image update at the switch, the switch boots utilizing a mini-DC module that reestablishes communication between the switch with the managing master switch and retries the image update.

    摘要翻译： 交换网络具有至少包括交换机和管理主交换机的多个交换机。 在管理主交换机上，从交换机接收到第一个能力向量（CV）。 管理主交换机确定第一个CV是否与记录交换网络中多个交换机的CV的网络成员资格数据结构中的至少第二个CV兼容。 响应于检测到不兼容性，管理主交换机启动对交换机的图像的图像更新。 为了响应交换机上的图像更新失败，开关使用小直流模块启动，该模块重新建立交换机与管理主交换机之间的通信，并重试映像更新。

    Scalable Virtual Appliance Cloud (SVAC) and Devices Usable in an SVAC
    82.
    发明申请
    Scalable Virtual Appliance Cloud (SVAC) and Devices Usable in an SVAC 有权
    可扩展虚拟设备云（SVAC）和在SVAC中可用的设备

    公开(公告)号：US20130247168A1

    公开(公告)日：2013-09-19

    申请号：US13423107

    申请日：2012-03-16

    申请人： Keshav G. Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    发明人： Keshav G. Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    IPC分类号： G06F21/00

    CPC分类号： H04L63/101 ,  G06F9/45558 ,  H04L45/64 ,  H04L47/125

    摘要： According to one embodiment, a system includes a scalable virtual appliance cloud (SVAC) comprising: at least one distributed line card (DLC); at least one switch fabric coupler (SFC) in communication with the at least one DLC; and at least one controller in communication with the at least one DLC, wherein one or more of the at least one DLC is an appliance DLC, wherein one or more of the at least one SFC is a central SFC, and wherein the SVAC appears to a device external of the SVAC as a single appliance device applying various services to a traffic flow.

    摘要翻译： 根据一个实施例，系统包括可伸缩虚拟设备云（SVAC），其包括：至少一个分布式线路卡（DLC）; 至少一个与所述至少一个DLC通信的交换结构耦合器（SFC）; 以及与所述至少一个DLC通信的至少一个控制器，其中所述至少一个DLC中的一个或多个是设备DLC，其中所述至少一个SFC中的一个或多个是中央SFC，并且其中所述SVAC看起来 作为将各种服务应用于业务流的单个设备设备的SVAC外部的设备。

    TECHNIQUES FOR EXECUTING THREADS IN A COMPUTING ENVIRONMENT
    83.
    发明申请
    TECHNIQUES FOR EXECUTING THREADS IN A COMPUTING ENVIRONMENT 审中-公开
    在计算环境中执行螺纹的技术

    公开(公告)号：US20120291034A1

    公开(公告)日：2012-11-15

    申请号：US13107896

    申请日：2011-05-14

    申请人： Dayavanti G. Kamath ,  Nirapada Ghosh ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy Pandey

    发明人： Dayavanti G. Kamath ,  Nirapada Ghosh ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy Pandey

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/4881 ,  G06F2209/486

    摘要： A technique for executing normally interruptible threads of a process in a non-preemptive manner includes in response to a first entry associated with a first message for a first thread reaching a head of a run queue, receiving, by the first thread, a first wake-up signal. In response to receiving the wake-up signal, the first thread waits for a global lock. In response to the first thread receiving the global lock, the first thread retrieves the first message from an associated message queue and processes the retrieved first message. In response to completing the processing of the first message, the first thread transmits a second wake-up signal to a second thread whose associated entry is next in the run queue. Finally, following the transmitting of the second wake-up signal, the first thread releases the global lock.

    摘要翻译： 用于以非预先方式执行进程的正常可中断线程的技术包括响应于与第一消息相关联的第一条目，用于第一线程到达运行队列的头部，由第一线程接收第一唤醒 -up信号。 响应于接收到唤醒信号，第一个线程等待一个全局锁定。 响应于接收全局锁的第一线程，第一线程从相关联的消息队列中检索第一消息并处理检索到的第一消息。 响应于完成第一消息的处理，第一线程向第二线程发送第二唤醒信号，该第二线程的相关条目在下一个运行队列中。 最后，在发送第二个唤醒信号之后，第一个线程释放全局锁定。

    Testing memories using algorithm selection
    86.
    发明申请
    Testing memories using algorithm selection 有权
    使用算法选择测试记忆

    公开(公告)号：US20050204231A1

    公开(公告)日：2005-09-15

    申请号：US10861851

    申请日：2004-06-04

    申请人： Nilanjan Mukherjee ,  Joseph Rayhawk ,  Amrendra Kumar

    发明人： Nilanjan Mukherjee ,  Joseph Rayhawk ,  Amrendra Kumar

    IPC分类号： G01R31/28 ,  G11C29/00

    CPC分类号： G11C29/10 ,  G11C29/14 ,  G11C29/16 ,  G11C29/38 ,  G11C2029/3202

    摘要： A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit is disclosed. In a specific example, a determination is made during running of a BIST whether one or more algorithms are to be run. If any algorithm is not designated for running, the particular algorithm is skipped and the test moves to other algorithms to be run. A BIST controller is configured to perform a group of test algorithms. Certain algorithms from the group may be checked to see if they are to be run or bypassed. A delay or skip state is desirably interposed following the inclusion of a particular algorithm and prior to the start of a next algorithm. A determination is made during the delay or skip state whether the next algorithm is to be run. The user may also have the option of running all of the algorithms if desired for performance of a particular BIST.

    摘要翻译： 公开了一种执行电路的至少一个存储元件的内置自检（BIST）的方法。 在具体示例中，在BIST的运行期间确定是否要运行一个或多个算法。 如果没有指定运算的算法，跳过特定的算法，并且测试移动到要运行的其他算法。 BIST控制器被配置为执行一组测试算法。 可以检查组中的某些算法，以查看它们是要运行还是旁路。 期望在包含特定算法之后并且在下一个算法开始之前插入延迟或跳过状态。 在延迟或跳过状态期间确定是否要运行下一个算法。 如果需要执行特定的BIST，用户还可以选择运行所有算法。

    Method for self-testing integrated circuits
    87.
    发明授权
    Method for self-testing integrated circuits 有权
    集成电路自检方法

    公开(公告)号：US06363506B1

    公开(公告)日：2002-03-26

    申请号：US09291448

    申请日：1999-04-13

    申请人： Ramesh Karri ,  Nilanjan Mukherjee

    发明人： Ramesh Karri ,  Nilanjan Mukherjee

    IPC分类号： G01R3128

    CPC分类号： G01R31/318371

    摘要： A versatile testing scheme provides both off-line and on-line integrated circuit testing using common test circuitry. The testing scheme generates test patterns, applies test patterns and compacts test responses to test the integrated circuit. The original design of the integrated circuit may be modified so that the functional units of the original design perform test operations during idle processing cycles in the normal mode of operation. To this end, functional units of the design may be constrained to perform the test function by coordinating the generation and application of the test patterns and the compaction of the test responses with a usage profile of the functional units.

    摘要翻译： 通用测试方案提供使用常用测试电路的离线和在线集成电路测试。 测试方案生成测试模式，应用测试模式和压缩测试响应来测试集成电路。 可以修改集成电路的原始设计，使得原始设计的功能单元在正常操作模式中的空闲处理周期期间执行测试操作。 为此，设计的功能单元可以被限制为通过协调测试模式的生成和应用以及测试响应的压缩与功能单元的使用简档来执行测试功能。

    MODIFYING A FINITE ELEMENT MESH
    88.
    发明申请
    MODIFYING A FINITE ELEMENT MESH 有权

    公开(公告)号：US20220067242A1

    公开(公告)日：2022-03-03

    申请号：US17412637

    申请日：2021-08-26

    申请人： Nilanjan Mukherjee ,  Jean Cabello ,  Jonathan Makem ,  Wafa Daldoul

    发明人： Nilanjan Mukherjee ,  Jean Cabello ,  Jonathan Makem ,  Wafa Daldoul

    IPC分类号： G06F30/23

    摘要： A computer-implemented method of modifying a finite element mesh. The method includes providing an original-input-orphan-mesh, selecting and extracting at least a part of the original-input-orphan-mesh as an orphan-element-patch-object, generating faces on the orphan-element-patch-object as a faces-on-mesh-object geometry, generating a new mesh patch element based on the faces-on-mesh-object-geometry and at least one changed meshing-parameter. The changed meshing-parameter is assigned to generate a new mesh patch element that is different to the corresponding original-input-orphan-mesh. The method further includes generating an amended orphan mesh by replacing the orphan-element-patch-object of the original-input-orphan-mesh by the new mesh patch element.

    Distributed link aggregation group (LAG) for a layer 2 fabric
    89.
    发明授权
    Distributed link aggregation group (LAG) for a layer 2 fabric 有权
    第2层结构的分布式链路聚合组（LAG）

    公开(公告)号：US09497073B2

    公开(公告)日：2016-11-15

    申请号：US13314455

    申请日：2011-12-08

    申请人： Dayavanti G. Kamath ,  Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    发明人： Dayavanti G. Kamath ,  Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    IPC分类号： H04L12/24 ,  H04L12/721 ,  H04L12/709 ,  H04L12/703

    CPC分类号： H04L41/0654 ,  H04L45/245 ,  H04L45/28 ,  H04L45/66 ,  Y02D50/30

    摘要： Each of first and second bridges of a data network having respective links to an external node implement a network bridge component that forwards traffic inside the data network and a virtual bridge component that forwards traffic outside of the data network. A virtual bridge is formed including the virtual bridge components of the first and second bridges and an interswitch link (ISL) between the virtual bridge components of the first and second bridges. Data frames are communicated with each of multiple external network nodes outside the data network via a respective one of multiple link aggregation groups all commonly supported by the virtual bridge.

    摘要翻译： 具有到外部节点的各个链接的数据网络的每个第一和第二桥接器实现转发数据网络内的业务的网桥组件，以及在数据网络之外转发业务的虚拟桥组件。 形成虚拟桥，包括第一和第二桥的虚拟桥组件和第一和第二桥的虚拟桥组件之间的交叉连接（ISL）。 数据帧通过虚拟桥通常支持的多个链路聚合组中的相应一个，与数据网络外部的多个外部网络节点中的每一个进行通信。