公开(公告)号：US08629017B2

公开(公告)日：2014-01-14

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US08298907B2

公开(公告)日：2012-10-30

申请号：US13323033

申请日：2011-12-12

申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/20

CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

公开(公告)号：US08193067B2

公开(公告)日：2012-06-05

申请号：US12630091

申请日：2009-12-03

申请人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

IPC分类号： H01L21/20

CPC分类号： H01L21/76224 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181

摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

摘要翻译： 公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。 形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。 在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。 因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。 在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

公开(公告)号：US08188528B2

公开(公告)日：2012-05-29

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US20120108050A1

公开(公告)日：2012-05-03

申请号：US13343850

申请日：2012-01-05

申请人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

发明人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L21/28

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.

摘要翻译： 嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。 具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly） 高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。 因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

公开(公告)号：US08008713B2

公开(公告)日：2011-08-30

申请号：US12410935

申请日：2009-03-25

申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

IPC分类号： H01L29/00

CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

公开(公告)号：US20110133310A1

公开(公告)日：2011-06-09

申请号：US12630091

申请日：2009-12-03

申请人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

IPC分类号： H01L29/92 ,  H01L21/8242

CPC分类号： H01L21/76224 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181

摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

摘要翻译： 公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。 形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。 在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。 因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。 在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

公开(公告)号：US20110042731A1

公开(公告)日：2011-02-24

申请号：US12545116

申请日：2009-08-21

申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8242

CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

公开(公告)号：US07888723B2

公开(公告)日：2011-02-15

申请号：US12016312

申请日：2008-01-18

申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

公开(公告)号：US20090315124A1

公开(公告)日：2009-12-24

申请号：US12141311

申请日：2008-06-18

申请人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

发明人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.

摘要翻译： 嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。 具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly） 高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。 因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。