公开(公告)号：US07411135B2

公开(公告)日：2008-08-12

申请号：US10711885

申请日：2004-10-12

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01R12/04

CPC分类号： H01L23/544 ,  H01L22/24 ,  H01L22/32 ,  H01L22/34 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49227 ,  H01L2224/45099

摘要： An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.

摘要翻译： 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。

公开(公告)号：US07405139B2

公开(公告)日：2008-07-29

申请号：US11462124

申请日：2006-08-03

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/322

CPC分类号： H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US20080146040A1

公开(公告)日：2008-06-19

申请号：US12041782

申请日：2008-03-04

申请人： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L21/31

CPC分类号： C23C16/04 ,  C23C16/513 ,  H01J37/32366

摘要： A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.

摘要翻译： 一种用于执行该方法的方法和装置。 该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及 （iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质 在基板上的预定区域形成膜的反应。

公开(公告)号：US20080122037A1

公开(公告)日：2008-05-29

申请号：US11462124

申请日：2006-08-03

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L29/34 ,  H01L21/66

CPC分类号： H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US20080099877A1

公开(公告)日：2008-05-01

申请号：US11553176

申请日：2006-10-26

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5258 ,  H01L23/5254 ,  H01L23/5256 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。

公开(公告)号：US07361581B2

公开(公告)日：2008-04-22

申请号：US10904677

申请日：2004-11-23

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC分类号： H01L21/44

CPC分类号： H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

摘要翻译： 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US07288475B2

公开(公告)日：2007-10-30

申请号：US11558959

申请日：2006-11-13

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

公开(公告)号：US20070158717A1

公开(公告)日：2007-07-12

申请号：US11306746

申请日：2006-01-10

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

公开(公告)号：US07207096B2

公开(公告)日：2007-04-24

申请号：US10707896

申请日：2004-01-22

申请人： Jeffrey P. Gambino ,  William T. Motsiff ,  Erick G. Walton

发明人： Jeffrey P. Gambino ,  William T. Motsiff ,  Erick G. Walton

IPC分类号： H01F7/127 ,  H01L21/44

CPC分类号： H01L28/10 ,  H01F41/041 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/4902 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for manufacturing high performance copper inductors includes providing a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal +1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal +1 level. The method includes integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal +1 wiring. Included are dielectric deposition and spacer formation steps, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.

摘要翻译： 一种用于制造高性能铜电感器的方法包括提供在最后的金属层面上形成的高Cu层压螺旋电感器，并且在最后的金属+1级别处，金属层通过棒与第二金属层相互螺旋形形成 最后一个金属级螺旋金属电感和最后一个金属+1电平。 该方法包括将厚电感器的形成与最后的金属+1布线形成接合焊盘，端子和互连布线。 包括介电沉积和间隔物形成步骤，和/或钝化金属如CoWP的选择性沉积，以钝化在最后一个金属层之后形成的Cu电感器。

公开(公告)号：US07169698B2

公开(公告)日：2007-01-30

申请号：US10707811

申请日：2004-01-14

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/311

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

摘要翻译： 本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。 刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。 或者，可以用包含SiO 2，SiCOH或掺杂硅酸盐玻璃的机械刚性电介质来加强互连结构的通孔区域。