公开(公告)号：US06929982B2

公开(公告)日：2005-08-16

申请号：US10915087

申请日：2004-08-10

申请人： Stephen M. Gates ,  Jeffrey C. Hedrick ,  Elbert E. Huang ,  Dirk Pfeiffer

发明人： Stephen M. Gates ,  Jeffrey C. Hedrick ,  Elbert E. Huang ,  Dirk Pfeiffer

IPC分类号： G03G13/06 ,  H01L20060101 ,  H01L21/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/44 ,  H01L23/48 ,  H05B6/64

CPC分类号： H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/316 ,  Y10S430/146 ,  Y10T428/31663

摘要： The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNwCxOyHz where 0.1≦v≦0.9, 0≦w≦0.5, 0.05≦x≦0.9, 0≦y≦0.5, 0.05≦z≦0.8 for v+w+x+y+z=1; forming a patterned photoresist atop the ceramic layer; patterning the ceramic layer to expose regions of the underlying substrate, where a remaining region of the underlying substrate is protected by the patterned ceramic layer; and etching the exposed region of the underlying substrate. Another aspect of the present invention is a buried etch stop layer having a composition of SivNwCxOyHz where 0.05

摘要翻译： 本发明包括一种用于形成硬掩模的方法，包括以下步骤：在基底顶上沉积聚合物预陶瓷前体膜; 将聚合物前陶瓷前体膜转化成至少一个陶瓷层，其中陶瓷层具有Si N x O x O x O O的组成， 其中0.1 <= v <= 0.9,0 <= w <= 0.5,0.05 <= x <= 0.9,0 <= y <= 0.5,0.05 对于v + w + x + y + z = 1，<= z <= 0.8; 在陶瓷层顶部形成图案化的光刻胶; 图案化陶瓷层以暴露下面的衬底的区域，其中下面的衬底的剩余区域被图案化的陶瓷层保护; 并蚀刻下面的衬底的暴露区域。 本发明的另一方面是具有下列组成的掩埋蚀刻停止层： 对于v + w + x + y +，0.05

公开(公告)号：US09075106B2

公开(公告)日：2015-07-07

申请号：US12512168

申请日：2009-07-30

申请人： Kerry Bernstein ,  James Culp ,  David F. Heidel ,  Dirk Pfeiffer ,  Anthony D. Polson ,  Peilin Song ,  Franco Stellari ,  Robert L. Wisnieff

发明人： Kerry Bernstein ,  James Culp ,  David F. Heidel ,  Dirk Pfeiffer ,  Anthony D. Polson ,  Peilin Song ,  Franco Stellari ,  Robert L. Wisnieff

IPC分类号： G06K9/00 ,  G01R31/311 ,  G01R31/00

CPC分类号： G01R31/311

摘要： An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

摘要翻译： 通过测量要测试的物理电路来获得待测试电路的发射图。 通过测量物理参考电路或通过模拟从参考电路预期的发射来获得参考电路的发射图。 与参考电路相比，要测试的电路的发射图与参考电路的发射图进行比较，以确定待测电路中的变化的存在。

公开(公告)号：US09054160B2

公开(公告)日：2015-06-09

申请号：US13088054

申请日：2011-04-15

申请人： Robert L. Bruce ,  Qinghuang Lin ,  Alshakim Nelson ,  Satyanarayana V. Nitta ,  Dirk Pfeiffer ,  Jitendra S. Rathore

发明人： Robert L. Bruce ,  Qinghuang Lin ,  Alshakim Nelson ,  Satyanarayana V. Nitta ,  Dirk Pfeiffer ,  Jitendra S. Rathore

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure includes a patterned and cured dielectric layer located directly on a surface of a patterned permanent antireflective coating. The patterned and cured dielectric layer and the permanent antireflective coating form shaped openings. The shaped openings include an inverse profile which narrows towards a top of the shaped openings. A conductive structure fills the shaped openings wherein the patterned and cured dielectric layer and the permanent antireflective coating each have a conductively filled region.

摘要翻译： 互连结构包括直接位于图案化的永久抗反射涂层的表面上的图案化和固化的电介质层。 图案化和固化的介电层和永久性抗反射涂层形成成形的开口。 成形的开口包括朝向成形开口的顶部变窄的反向轮廓。 导电结构填充成形开口，其中图案化和固化的介电层和永久性抗反射涂层各自具有导电填充区域。

公开(公告)号：US08916978B2

公开(公告)日：2014-12-23

申请号：US13613890

申请日：2012-09-13

申请人： Qinghuang Lin ,  Dirk Pfeiffer ,  Ratnam Sooriyakumaran

发明人： Qinghuang Lin ,  Dirk Pfeiffer ,  Ratnam Sooriyakumaran

IPC分类号： H01L23/52 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/768 ,  G03F7/00 ,  H01L21/311 ,  G03F7/40

CPC分类号： H01L23/5329 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/02123 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/743 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.

摘要翻译： 提供一种互连结构，其包括半导体衬底; 图案化和固化的光致抗蚀剂，其中光致抗蚀剂含有低k电介质替代物，并且在其顶部和侧壁表面上包含形成通孔或沟槽的强化层; 以及通孔或沟槽中的导电填充材料。 还提供了一种用于制造互连结构的方法，其包括在半导体衬底上沉积光致抗蚀剂，其中光致抗蚀剂含有低k电介质成分; 将光刻胶成像曝光于光化辐射; 然后在光致抗蚀剂中形成通孔或沟槽的图案; 表面强化通孔或沟槽的图案，证明通孔或沟槽的顶部和侧壁上的强化层; 固化通孔或沟槽的图案，从而将光致抗蚀剂转化为电介质; 并用导电填充材料填充通孔和沟槽。

公开(公告)号：US08759976B2

公开(公告)日：2014-06-24

申请号：US13570972

申请日：2012-08-09

申请人： Daniel C. Edelstein ,  Gregory M. Fritz ,  Stephen M. Gates ,  Dirk Pfeiffer

发明人： Daniel C. Edelstein ,  Gregory M. Fritz ,  Stephen M. Gates ,  Dirk Pfeiffer

IPC分类号： H01L23/485

CPC分类号： H01L23/5228 ,  H01L21/0332 ,  H01L21/32139 ,  H01L23/52 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H01L2924/00

摘要： A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.

摘要翻译： 提供一种包括具有非重复随机形状作为物理不可克隆功能（PUF）的多个亚光刻导体特征的安全电子结构以及包括该非亚光刻导体特征的集成电路。 多个导体特征中的一些导体特征形成欧姆电接触到位于具有非重复形状的多个导体特征的上方或下方的规则间隔的导体阵列的一部分，而多个导体特征的其它导体特征 导体特征不与任何规则间隔的导体阵列形成欧姆电接触。 因此，提供了可以在集成电路内用作PUF的电连续性的唯一签名。

公开(公告)号：US20140042627A1

公开(公告)日：2014-02-13

申请号：US13570968

申请日：2012-08-09

申请人： Daniel C. Edelstein ,  Gregory M. Fritz ,  Stephen M. Gates ,  Dirk Pfeiffer

发明人： Daniel C. Edelstein ,  Gregory M. Fritz ,  Stephen M. Gates ,  Dirk Pfeiffer

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/57 ,  G06F21/73 ,  G09C1/00 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5228 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H01L2924/00

摘要： A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.

摘要翻译： 提供了一种安全的电子结构，其包括作为物理不可克隆功能（PUF）的通孔阵列。 具体地，安全电子结构包括位于第一规则间隔的导体阵列的较低电平和第二规则间隔的导体阵列的较高电平之间的电接触通孔的阵列。 通孔阵列的每个电接触通孔通过下层中的第一规则间隔的导体阵列和上层中的第二规则间隔的导体阵列单独寻址，并且具有电阻值。 每个电接触通孔的每个电阻值形成电阻值的分布，其中电阻值的分布是随机的。 电接触通孔阵列的电阻值的这种随机分布可以用作本公开的电子结构中的物理不可克隆功能。

公开(公告)号：US08525169B1

公开(公告)日：2013-09-03

申请号：US13572289

申请日：2012-08-10

申请人： Daniel C. Edelstein ,  Stephen M. Gates ,  Edward W. Kiewra ,  Satyanarayana V. Nitta ,  Ramachandran Muralidhar ,  Dirk Pfeiffer

发明人： Daniel C. Edelstein ,  Stephen M. Gates ,  Edward W. Kiewra ,  Satyanarayana V. Nitta ,  Ramachandran Muralidhar ,  Dirk Pfeiffer

IPC分类号： H01L21/66 ,  H01L21/74

CPC分类号： H01L23/544 ,  H01L21/268 ,  H01L21/76894 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53271 ,  H01L23/573 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2924/0002 ,  H04L9/3247 ,  H04L9/3278 ,  H01L2924/00

摘要： The present disclosure relates to a secure device having a physical unclonable function. The device includes an integrated circuit having a semiconducting material in at least one via in a backend of the integrated circuit. The present disclosure also relates to a method for manufacturing a secure device having a physical unclonable function. The method includes providing an integrated circuit and adding a semiconducting material to at least one via in a backend of the integrated circuit. In some instances a property of the semiconducting material in the at least one via is measured to derive a signature.

摘要翻译： 本公开涉及具有物理不可克隆功能的安全装置。 该器件包括在集成电路的后端中的至少一个通孔中具有半导体材料的集成电路。 本公开还涉及一种用于制造具有物理不可克隆功能的安全装置的方法。 该方法包括提供集成电路并将集成电路的后端中的至少一个通孔添加半导体材料。 在一些情况下，测量至少一个通孔中的半导体材料的特性以导出签名。

公开(公告)号：US20120092633A1

公开(公告)日：2012-04-19

申请号：US13324092

申请日：2011-12-13

申请人： Kafai Lai ,  Dirk Pfeiffer ,  Alan E. Rosenbluth

发明人： Kafai Lai ,  Dirk Pfeiffer ,  Alan E. Rosenbluth

IPC分类号： G03B27/42

CPC分类号： G03F7/70216

摘要： A system for exposing a resist layer to an image that includes a layer reflective to imaging tool radiation and a resist layer having a region of photosensitivity over the reflective layer. An imaging tool projects radiation containing an aerial image onto the resist layer, with a portion of the radiation containing the aerial image passing through the resist and reflecting back to the resist to form an interference pattern of the projected aerial image through the resist layer thickness. The thickness and location of the resist layer region of photosensitivity are selected to include from within the interference pattern higher contrast portions of the interference pattern in the direction of the resist thickness, and to exclude lower contrast portions of the interference pattern in the resist thickness direction from said resist layer region of photosensitivity, to improve contrast of the aerial image in said resist layer region of photosensitivity.

摘要翻译： 一种用于将抗蚀剂层暴露于包括反射成像工具辐射的层的图像和在反射层上具有光敏区域的抗蚀剂层的系统。 成像工具将包含空间图像的辐射投射到抗蚀剂层上，其中包含空间图像的辐射的一部分穿过抗蚀剂并反射回抗蚀剂，以形成通过抗蚀剂层厚度的投影空间图像的干涉图案。 光敏层的抗蚀剂层区域的厚度和位置被选择为在干涉图形之中包括在抗蚀剂厚度方向上的干涉图案的较高对比度部分，并且排除抗蚀剂厚度方向上的干涉图案的较低对比度部分 从所述抗蚀剂层区域的光敏性，改善所述抗蚀剂层区域中的空间像的光敏性的对比度。

公开(公告)号：US08137997B2

公开(公告)日：2012-03-20

申请号：US12787429

申请日：2010-05-26

申请人： Matthew E. Colburn ,  Theodore G. van Kessel ,  Yves C. Martin ,  Dirk Pfeiffer

发明人： Matthew E. Colburn ,  Theodore G. van Kessel ,  Yves C. Martin ,  Dirk Pfeiffer

IPC分类号： H01L21/00

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： A system for imprint lithography, which includes a substrate, a patterned mask, an imprint applying unit that imprints, via the patterned mask, a pattern into a resist layer on the substrate, and an overlay device that overlays a cladding layer over the substrate.

摘要翻译： 一种用于压印光刻的系统，其包括衬底，图案化掩模，压印施加单元，其通过图案化掩模将图案压印到衬底上的抗蚀剂层中，以及覆盖器件，覆盖衬底上的覆层。